Thursday, May 25, 2017

An FPGA SDR HF Transceiver, Part 6 -- Schematics, Main Board

In this sixth blog post in my FPGA SDR Transceiver series, I will begin describing the radio's Hardware, specifically (in this post), the Main Board, which contains the FPGA, ADC, DAC, Audio Codec, and support circuitry.

(Part 5 of this series is here: Part 5)

But before I begin, let me again acknowledge Dick Benson, W1QG.  Dick is the father of this design, and although I've made some modifications to the FPGA logic, the underlying FPGA architecture and the vast majority of the Simulink implementation is Dick's.

A note regarding the schematics...

These schematics were drawn using the Lite version of Cadence's Orcad Capture.  This is the free version of the program, and it limits a schematic's number of nets to 75 and the number of parts to 60 (limitations which apply if you want to save the design, which I always do).

Because this radio design has many more nets and parts than the 75/60 limit specified by Cadence, I have broken the overall design into smaller "bite size" schematics, each  independent of the others and each drawn on a single A-size sheet.

But because I've broken up the design into smaller independent pieces, I can not use Capture's Design Rule Checker to check the overall design for design flaws.  Therefore, there is the possibility that errors have crept into the schematics.  So be aware!

A Note on Logic Levels:

A number of different logic families and devices are used in this radio.  I want to ensure that input logic thresholds and output logic drive levels are compatible with each other.  The spreadsheet below summarizes the different specifications:

(Click on image to enlarge)

Notes on Logic Levels:
  1. The Xilinx output voltages aren't high enough to meet the worst-case Arduino Input Level specification, so their levels will need to be shifted if driving Arduino inputs (this level-shifting is done in the Front Panel circuitry).
  2. 2N7000 devices make for simple I/O drivers (e.g. relay drivers, etc.)  But their worst-case Vgs is 3V.  This value is sufficient when driven with output levels from 5V devices (e.g. Arduino), but it is above worst-case Xilinx drive levels.  For this reason I will use bipolar transistors (rather than 2N7000 transistors) for I/O interfacing, when needed.
  3. The 74VCX245 transceiver is the output driver for the LTC DC918C ADC demo board.  It is powered by 2.5 VDC, and its outputs drive the Xilinx FPGA.

Now, let's look at the overall Block Diagram of the FPGA SDR radio...

FPGA SDR Block Diagram:

(Click on image to enlarge)

The Main Board, which is the subject of this blog post, incorporates the FPGA, RF ADC, RF DAC, Audio Codec, Speaker Amplifier, and various miscellaneous support and interface circuits.  It is the processing heart of the radio.

Notes on this block diagram:
  1. The T/R relay, when un-energized (OFF), shorts the receiver's input to ground, protecting the receiver input circuitry when the radio is off.
  2. Various interfaces are shown to external devices.  These interfaces will be explained further, below.
  3. All other circuitry not ON the Main Board will be described in future blog posts.
  4. Schematics and circuitry might change, as determined by design checkout.

Block Diagram, Main Board:

(Click on image to enlarge)

And below are some pictures of the Main Board in its Rev. A implementation:

Top Side

Bottom Side

And now, let's discuss the Main Board's hardware....

Hardware Design, Main Board:

Schematic, ADC Input:

(Click on image to enlarge)

Notes on ADC Input schematic:
  1. This radio uses a Linear Technology Demo Board (the DC918C, version C, incorporating an 80 MHz, 16-bit LTC2206 ADC) for the RF ADC.
  2. The DC918C's output drivers are 74LVX245 Buffers whose VCC is 2.46 volts (via an LT1763 LDO regulator).  Therefore, the maximum high-level voltage from the board to the Xilinx inputs is about 2.26 volts (assuming 100uA worse-case output current -- this voltage falls as output current increases).  With drive current at about 6 mA, the output voltage level is just within Xilinx input threshold specification, with the margin vanishingly small if using the Xilinx LVCMOS33 spec, but better with the LVCMOS25 spec.
  3. 12 VDC power comes in to the radio on this page.  It is converted down to 5V using a simple LM2576 buck regulator, and it is this 5V power buss which sources power for the 3.3V LDO regulators used throughout this design.
For reference, here is the schematic of the LTC DC918C ADC Demo board that Dick and I use in our radios.  The table in the lower left-hand corner specifies component values for the different board versions, including the -C version used by us:

(Click on image to enlarge)

Notes on the DC918C ADC Demo Board:
  1. Dick and I use the DC918C-C version of the DC918C Demo Board (80 MHz LTC2206).  No modifications were made to this board.
  2. Schematics and other design files for the DC918C-C board can be found at the Linear Technology site:
  3. LTC2206 Documentation can be found here:
  4. The DC918C-C's on-board jumpers are set as follows:
    • JP1:  Set to GND, not OVP.
    • JP2 (SENSE):  Set to VDD, not OPEN.
    • JP3 (PGA):  Set to VDD, not GND.
    • JP4 (RAND):  Set to GND, not VDD.
    • JP5 (SHDN):  Set to GND, not VDD.
    • JP6 (DITH):  Set to GND, not VDD.

Schematic, Clock and Misc.:

(Click on image to enlarge)

Notes on Clock and Misc.:
  1. The 80 MHz clock source is a Conner-Winfield TCXO (available from Digikey), part number TB522-080.0M.  (LVCMOS outputs, 3.3Vdc).
  2. This TCXO drives a 74AC04 inverter whose input has been biased to mid-scale DC (1.65V) and which is AC-coupled to the TXCO output.  This inverter, in turn drives other 'AC04 inverters which act as clock drivers, so that the FPGA clock, the ADC clock, and the DAC clock are driven independently.  Thus, there is no clock daisy-chaining.
  3. R11 and R10 slightly roll off the clock edges to reduce ringing.
  4. J1 is the 26-pin header to connect the radio's Front Panel to the Main Board.
  5. Note that because the Front Panel's Arduino's output levels are referenced to the Arduino's 5V power, R5 and R6 drop the Arduino output voltages down to a level more compatible with the Xilinx input levels.
  6. R9 and C14 filter (and scale) the S-Meter PWM signal.  Note that the meter is 1mA Full Scale.
  7. Q1 (open-collector inverter) can be used by the Front Panel (Arduino) to Reset the FPGA.  For example, this is used if the Command Interface gets out of sync.
  8. The oscillator and 74AC04 are powered by the same 3.3V regulator used to power the LTC 918C-C ADC board.  (This regulator also powers the Audio Codec).

Schematic, Xilinx FPGA Board:

(Click on image to enlarge)

Notes on Xilinx FPGA Board:
  1. Dick and I use a Waveshare Core3S500E Xilinx Development Board to simplify the FPGA hardware implementation (no need to solder an FPGA!).
  2. This schematic page defines which pins of the Waveshare Core3S500E board are used in this radio.
  3. I disabled the on-board 50 MHz oscillator by grounding its output-enable pin (pin 1), thus allowing the external 80 MHz clock to be connected to this oscillator's pin 3.  (Note that pin 1 in the Waveshore partial-schematic, below, is simply called "NC".  It actually is the oscillator's OE pin.)
  4. FPGA outputs TX_ATTEN_0 and TX_ATTEN_1 are not yet used in the design.  I've included them in case I would like some way to change TX gain apart from adjusting the TX_Level within the FPGA.  For example, these two bits could select different values for the DAC's full-scale current resistor.
  5. My modifications to this board are described below:
Mods to Waveshare Core3S500E Xilinx Core Board:

(Click on image to enlarge)

Notes on Mods to the Waveshare Core3S500E:
  1. Additional information on the Waveshare Core3S500E board can be found here:

Schematic, DAC Out:

(Click on image to enlarge)

Notes on DAC Output:
  1. The DAC is an AD9744 14-bid ADC
  2. I use a separate 3.3V regulator for the DAC (to minimize possible noise injection into the DAC via its VCC pin if this regulator were also powering other devices).
  3. R1 sets the full-scale output current.  With 2K ohms, full-scale current is 19.2 mA +/-5%, assuming R1 is 1%, given the spec'd range of VREFIO.
  4. IFS = 32*VREFIO/R1 = 32*1.2/R1.

Schematic, Audio Codec:

(Click on image to enlarge)

Notes on Audio Codec:
  1. The Audio Codec is an AKM AK4554 16-bit stereo audio codec.
  2. FPGA outputs driving this Codec are lightly filtered (e.g. R4/C17), to round off edges and thus lower harmonic energy (just in case they might be picked up by the receiver).  Note -- strictly speaking, these 1-pole filters might not be needed in this design, but I got into the habit of using them long ago to help ensure that products I designed met EN61000 EMC standards.  You'll see me use this technique throughout this design.
  3. All inputs (or outputs) to/from the outside world (e.g. Mic In, Line In, and Codec Right Out) are protected with TVS devices and series-resistors at the inputs (the latter to limit transient current).
  4. The Codec left-channel output first drives a low-pass filter (four-pole, cutoff at 4.9 KHz, gain of 1) which is between it and the input of the Speaker Amplifier.
  5. R1 (33K) sets the voltage gain of U2 (the Speaker Amplifier, a TPA0211 device) to 3.8 (= 125K/33K), which ensures that at the maximum Codec output (1.98 Vpp), the amplifier's drive into a 4-ohm speaker load will be about 1.8 watts RMS -- just below 2 watts, above which amplifier distortion increases significantly, per the TPA0211 datasheet.
  6. I jumper J5 pin 3 to J5 pin 4 (I am not using the originally planned-for functionality of J5).
  7. The primary function of C11 (510 pF) is to shunt RF (to hopefully minimize RF susceptibility).
  8. This design originally used a TI PCM3008 codec.  But the TI codec has greater out-of-band noise compared to the AK4554 (which is pin-for-pin compatible with the PCM3008), as the following image demonstrates:
(Click on image to enlarge)

Schematics, Codec Four-Pole Lowpass Filter:

(Click on image to enlarge)

Notes on Codec Four-Pole Lowpass Filter:

  1. Two op-amp, four pole Sallen-Key Lowpass Filter (Fc = 4.9 KHz, Av = 1).  I used this website:
  2. Because the LMC662 op-amps are powered only by a positive voltage, the input signal must have a DC offset.  This offset is provided by the AK4554 codec (offset at 1/2 of VDD, or 1.65 VDC for a VDD of 3.3V).  (Note that the max codec output, given a VDD or 3.3V, will be 1.98 Vpp for a typical AK4554).
  3. The LMC662 is powered by 12V (rather than 5V), because worst-case Common-Mode input range (V+ - 2.4V for the LMC662C), coupled with worst-case codec output positive swing (2.18 V, max) could have been an issue if the LMC662 had been powered with 5V (admittedly, it is an issue by only 0.08V, but given that 12V was readily available (actually, 14.5 VDC) , why not use that?).
  4. Here is a plot of the LPF's measured frequency response:
(Click on image to enlarge)

Schematic, Interconnects 1:

(Click on image to enlarge)

Notes on Interconnects 1:
  1. A separate 3.3V regulator is used to power the board's various interface circuitry (on this schematic page and the next 3 "Interconnects" pages).
  2. External I/O: EXT. IN and EXT. OUT usage is yet to-be-defined.  I've included this I/O in the design "just in case" I find a need for it later.
  3. EXT_IN should not be driven higher than 3.3V -- TVS1 will protect it from over-voltage (current-limited by R7).  And in the event of a large, positive-going transient event, D7 should prevent Q2's base-emitter junction from being damaged by an accidentally high reverse-bias Vbe voltage. (And note that EXT. IN will source power (3.3V dropped by Q2's Vbe, D2, and R7, so must ensure that devices attached to this pin will not be harmed by this current when they are powered off).
  4. Controls for an external Receive Attenuator are included.  This attenuator might be a Mini-Circuits DAT-31A-SP+ Digital Attenuator, but it could be something else, as long as I can set attenuation with 3 bits.
  5. I've included an EXT. PA T/R relay-closure output for controlling external power amplifiers such as my SB-220 or AL-811.

Schematic, Interconnects 2:

(Click on image to enlarge)

Notes on Interconnects 2:
  1. This page contains an interface for communicating with my Automatic Antenna Tuner.  This is a bit like putting the cart before the horse, because I don't have a corresponding interface in the Tuner.  Never the less, someday there might be one!  And in anticipation of that event I thought I'd add the circuitry here.  (Note:  the interface has since been implemented!  See part 11 of this blog series).
  2. The Interface is pretty much self explanatory.  The signals to the outside world have TVS with current-limiting resistors for over-voltage protection.  And RF bypassing with small caps.
  3. Also, output filtering for three FPGA outputs is shown on this page -- these three filters were originally on the FPGA schematic page, but their inclusion there meant that the schematic exceeded the Orcad Lite's limits on nets/parts, so I moved them here.

Schematic, Interconnects 3:

(Click on image to enlarge)

Notes on Interconnects 3:
  1. I hope to incorporate a Flex-radio SDR-1000 PA module that I have into this radio to give it 100 watts out.  Details are sketchy at the moment -- this PA might be mounted inside this radio's chassis, or it might be mounted in a separate case (so that it could be used for other purposes when not used for this radio.  The important point is -- nothing is yet finalized!  If the PA ends up in a separate case, I will probably use a 25-pin D-connector to connect that chassis to this radio  -- using ribbon cable between the two units with ground between each signal will help reduce EMI susceptibility.  Thus, the reason for J3.
  2. Assuming the SDR-1000 PA performs as I hope it will, I will describe in a later post how it connects to this radio.
  3. Open-collector drivers communicating between this radio and the PA provide a very simple interface between boards with different logic voltages (e.g. the radio's 3.3V digital power versus the PA's 5V digital power) -- no level-shifting required.
  4. ESD protection of the signals driven by the ULN2003A is provided, for positive-going pulses, by TVS2, connected to U1's internal clamping diodes.  Although I've never tried ESD protection this way, it seems to me it should work, and it saves parts, as I don't need a TVS device for each line. Negative-going pulses are clamped by internal clamp diodes (within the ULN2003) between the output pins and ground.

Schematic, Interconnects 4:

(Click on image to enlarge)

Notes on Interconnects 4:
  1. A future project of mine is a 500 watt external PA.  This interface would allow the FPGA SDR radio to set automatically the PA's output filters, etc.  Note this interface's similarity to the SDR-1000 interface, above.
  2. I've added an extra PA Filter-selection signal (nFilt_F3), in case I need to specify separate, rather than combined, filters (e.g. the SDR-1000 PA combines 10 and 12 meters into a common filter, but I might find that I need to separate these filters into two separate filters, rather than one combined filter, in the 500 watt PA).
  3. Due to Orcad Lite's net and part limitations, the SW1 and SW2 are shown on this page rather than on the FPGA page.

Construction Notes:

This board was built on a piece of scrap double-sided FR4 PCB stock.  Very handy, and it provides an excellent ground plane.  I cut holes in it to mount the FPGA board so that I could easily access both sides of this board, as well as to mount an Electroboard prototyping board with the AD9744 DAC soldered to it.  (I also use one of their prototyping boards to mount the PCM3008 codec, but I did not cut a hole into the main board -- instead, this prototyping board is soldered to the top ground plane of the main board).

For mounting small parts, I often used small rectangles I had cut from a larger BusBoard Prototyping Systems prototyping board.  These are great for mounting small SMD devices,  relays, and even ULN2003A DIP ICs.

And at times I also carved pads out of the copper plane on either side of the main PCB (depending upon which side it made sense to mount the components), using a Dremel tool and a 30 degree, 0.1mm Tip Diameter Conical Engravers Cutter V-bit.  You can see an example of this, above, for the 3.3V LDO regulator used to power the interface circuitry.

That's it for this blog post!

Background Notes:

SDR Notes:  Weaver Modulation and Demodulation
SDR Notes:  The Mixer Mathematics of Digital Down Conversion

Posts in this Series:

Part 1: Overview
Part 2: FPGA Modulation and Demodulation
Part 3: Interpolation and Decimation Filters
Part 5: Control Interface, Etc.
Part 9: 50 dB HF RF Power Amplifier

Standard Caveat:

I or Dick might have made a mistake in our designs, equations, schematics, models, etc.  If anything looks confusing or wrong to you, please feel free to comment below or send me an email.

Also, I will note:

This design and any associated information is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

Thursday, May 4, 2017

An FPGA SDR HF Transceiver, Part 5 -- Control Interface, Etc.

In this fifth blog post in my FPGA SDR Transceiver series, I will conclude the discussion of the FPGA logic with a description of the Control Interface and any other miscellaneous circuitry I have not yet mentioned.

(Part 4 of this series is here: Part 4)

But before I begin, let me again acknowledge Dick Benson, W1QG.  Dick is the father of this design, and although I've made some modifications to the FPGA logic, the underlying architecture and the vast majority of the Simulink implementation is Dick's.

Control Interface:

The Control Interface circuitry (also known as the Serial Interface, and sometimes even called the Command Interface by me) is the serial interface through which the FPGA can be controlled by an external processor, for example a PIC or an Arduino.

Let's call this external processor the Control Processor.

This Control Interface consists of 4 signals (plus a fifth, the Interrupt/Overload signal, which will be discussed later in this blog):
  • Cntrl_Data (Serial Data, Input to FPGA)
  • Serial_Out (Serial Data, Output from FPGA)
  • Cntrl_Clk (Serial Clock, Input to FPGA)
  • RFD (Request for Data, Output from FPGA)
Data is transferred serially between the FPGA and the Control Processor, and the Control Processor is the master of this data transfer, clocking the data synchronously via Cntrl_Clk.

The serial data words are 32 bits long, and so 32 clocks are required to complete a word-transfer to or from the FPGA.

RFD identifies when the FPGA's Serial Interface circuitry is ready to receive (or send) the first bit of a thirty-two bit data word.  It ensures that the FPGA's internal Control Interface circuitry and the external Control Processor remain in sync.  (If they should get out of sync, the Control Processor can force the interface to reset using the FPGA's external nRST signal).

The thirty-two bit Cntrl_Data word sent to the FPGA is divided into two fields:
  • Address Field, 6 bits -- these are the 6 LSB's of the Cntrl_Data word.
  • Data Field, 26 bits -- these are the 26 MSB's of the Cntrl_Data word.

The 32-bit Cntrl_Data word is clocked into the FPGA MSB first.  Therefore, the address bits are the last bits to arrive into the FPGA.

Upon reception of all 32 bits, the 26 bits representing the Data field will be automatically clocked into the FPGA register addressed by the 6-bit Address field.

A thirty-two bit data word, Serial_Out, is also sent from the FPGA to the Control Processor.  This word contains information such as the revision of the FPGA's configuration code, Overload status, and the state of FPGA General-Purpose inputs.

Because there is only one 32-bit Serial_Out data word, then strictly speaking, no address is required.  In fact, this word is clocked out simultaneously whenever any Cntrl_Data word is written to the FPGA.  However, to allow the Control Processor to read the Serial_Out data word without also having to simultaneously write to an existing register, address 63 (0x3F) has been defined to be a dummy address with no writable register.

Therefore, to receive the Serial_Out data word without worry of updating an FPGA register, the Control Processor can simply write to address 63.

Unlike the Cntrl_Data word, which is clocked into the FPGA MSB first, the Serial_Out word is clocked out of the FPGA LSB first.

Both Cntrl_Clk and Cntrl_Data, as inputs into the FPGA, are sampled and synchronized within the FPGA to an internal clock of 10 MHz (80 MHz divided by 8).  Therefore, the Control Processor should ensure that Cntrl_Clk runs at a slower clock rate so that its transitions can be detected by the FPGA.

One final note:  Cntrl_Data is clocked into the FPGA on the rising edge of Cntrl_Clk.  And Serial_Out output data will also change on the rising edge of Cntrl_Clk.

Let's look more closely at the Control Interface circuitry.  It is contained within the "Serial_Interface1" subsystem of the Simulink Model.  I have highlighted it below, in yellow.

(Click on image to enlarge)

Opening up the Serial_Interface1 subsystem, we see:

(Click on image to enlarge)

Let's look more closely at these subsystems.  I will highlight each subsystem in turn...


The Serial_In_Parallel_Out subsystem is highlighted below.

(Click on image to enlarge)

This subsystem receives the incoming Cntrl_Data serial data stream and converts it into parallel format.  It also counts the serial bits as they arrive, and this same counter selects which bit of the 32-bit Serial_Out output word to present (as serial data) at the FPGA's Serial_Out pin.

Opening up Serial_In_Parallel_Out subsystem and the subsystems contained within it:

(Click on image to enlarge)

(Click on image to enlarge)

(Click on image to enlarge)

(Click on image to enlarge)

  • The Valid bit goes high for one clock after all 32 bits of a data word have been clocked into (or out of) the FPGA.  It is used to create the appropriate Write Enable to load the addressed FPGA register (see Address Decode block, below).
  • Par_26 is the 26-bit Data field (in parallel format).
  • Address_6 is the 6-bit address field.
  • Index is a 5-bit value to select which bit of the 32-bit Serial_Out word should be inserted into the output serial data stream.

Address Decode:

The Address Decode block is highlighted in yellow, below.

(Click on image to enlarge)

The Address Decode block decodes the 6 address bits contained within the 32 bit Cntrl_Data word and generates a Write Enable signal for each address.

(Click on image to enlarge)

General-Purpose Outputs:

The General Purpose Outputs block is highlighted in yellow, below.

(Click on image to enlarge)

The register in this block is loaded when its Write Enable, WR_GP_REG, is high.  The 26-bit data field is divided into the following subfields:
  • Bits 11-0:  DOUT_0to11:  Output bits sent to FPGA General Purpose output pins.  They can be used for driving external relays, etc.
  • Bits 16-12:  IRPT_EN0to4:  Interrupt Enables which enable any of five possible interrupt inputs to generate an Interrupt to the Control Processor.
  • Bit 17:  P23_SEL:  Selects if FPGA Pin 23 (an FPGA output, sent to the Control Processor) represents an Interrupt or an Overload condition.
(Click on image to enlarge)

Interrupt Generator:

The Interrupt Generator is highlighted in yellow, below:

(Click on image to enlarge)

The Interrupt Generator can generate an interrupt signal to interrupt the external Control Processor.

There are five possible interrupt sources.  Four are the General Purpose FPGA inputs, and the fifth interrupt goes active upon a transition of any of five Overload conditions.

The five interrupts  can be individually enabled or disabled.  If enabled, any change in a signal's state (from high to low or low to high) will generate an interrupt.

If the Control Processor receives an interrupt, it should read the Interrupt Status via address 63 (data format is described later, below).  At the completion of this read any interrupt that is set will be reset.

(Click on image to enlarge)

(Click on image to enlarge)

Parallel-to-Serial Output:

The Parallel-to-Serial block is highlighted below, in yellow:

(Click on image to enlarge)

This block creates the 32-bit Serial_Out serial data stream that is sent from the FPGA to the Control Processor.

This serial-data stream is sent to the Control Processor whenever the Control Processor writes to an FPGA register (note that a write to address 63 sends this stream to the Control Processor without an actual register being written to).

The 32-bit field of the Serial_Out word has the following subfields:

o  Bits 7-0:  FPGA Code Version (set by the user in the Top Level of the Simulink Model, and it is used to identify the revision of the FPGA code).

o  Bits 11-8:  Four General Purpose Inputs, to allow the Control Processor to monitor external signals via the FPGA.

o  Bits 16-12:  Five Interrupt-Status bits.  Four Interrupts are generated by the four General Purpose Inputs, and the fifth is generated by any of the Overload bits within the FPGA.

o  Bits 19-17:  Not used (set to 0).

o  Bits 24-20:  State of the five Overload bits.  These Overload bits are:
  • Bit 20:  ADC/DAC Overload
  • Bit 21:  Codec Overload
  • Bit 22:  AM Overmod
  • Bit 23:  CIC Overload
  • Bit 24:  DA Overload
(Note that the five Overload bits are automatically cleared after the Control Processor receives the Serial_Out data.)

o  Bits 31-25:  Not used (set to 0)

(Click on image to enlarge)

Pin 23:

The FPGA's pin 23 (called "P23 in the Simulink Model) is an output pin that can be considered a "fifth" signal of the Control Interface.  Its circuitry is highlighted in yellow, below:

(Click on image to enlarge)

This pin can have two meanings:

1.  If the P23_SEL signal from the GP_Outputs block is low, then Pin 23 simply represents an "NOR'ing" of the 5 Overload bits -- that is, if Pin 23 is low, then one (or more) of the five overload bits is high (i.e. in the state of overload).

2.  If P23_SEL is high, then Pin 23 represents the Interrupt signal from the Interrupt_Generator block, and it is used to interrupt the Control Panel's processor.

Clock Divider:

The final Simulink FPGA SDR logic block to discuss is the Clock Divider, highlighted below, in yellow:

(Click on image to enlarge)

The Clock Divider simply divides down the 80 MHz clock to create three clocks that, driving FPGA output pins, can be used to clock external circuity, should the need arise.  These three clocks are:  20 MHz, 10 MHz, and 5 MHz.

(Click on image to enlarge)

Dick originally added this circuitry so that he could create an external phase-locked loop to lock the radio's clock to an external frequency reference.  Per Dick...

Since day 1, I have used the divide-by-sixteen that produces the 5MHz. The 80 MHz Crystal Oscillator that generates the FPGA clock is locked to a 5MHz TCXO using this signal.

The only thing I have not done is put in way to switch out the internal 5 MHz TCXO with an external 5 or 10 MHz Frequency Reference input from the back panel.

The TCXO is so good  (a few Hz +/- at 28 MHz) the external reference is just not justified.   

That's it for the FPGA description!  In my next post, I will begin discussing the hardware design of the radio.

Background Notes:

SDR Notes:  Weaver Modulation and Demodulation
SDR Notes:  The Mixer Mathematics of Digital Down Conversion

Posts in this Series:

Part 1: Overview
Part 2: FPGA Modulation and Demodulation
Part 3: Interpolation and Decimation Filters
Part 5: Control Interface, Etc.

Standard Caveat:

I or Dick might have made a mistake in our designs, equations, schematics, models, etc.  If anything looks confusing or wrong to you, please feel free to comment below or send me an email.

Also, I will note:

This design and any associated information is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.