Saturday, January 29, 2011

Building an 80-Meter Class E/F RF Amplifier...

After simulating on my computer an 80-Meter Class E/F amplifier (here and here), I decided to actually build one. Here it is:

(Click on image to enlarge)

With a 26V power supply, RF Power Out is about 40 watts. And efficiency of the MOSFET final is in the range of 85-95% (depending upon which power meter I use to measure RF power).

In the image above:
  • The two MOSFETs (IRF530, N-Channel) are mounted on the vertical copper plate at the upper-left.
  • The Tank circuit, including the transformer (5-turn air-wound coil) and a variable air capacitor (for tuning the tank) are at the upper-middle.
  • Control logic (and Symmetry adjustment potentiometers) are at the middle-left.
  • Two solenoid-style inductors (MOSFET Drain DC feeds) are lower middle.
  • A 12V switching voltage-regulator is at the lower-right (with the large toroidal inductor).
  • You can also see the two scope-probes attached to the MOSFET Drain busses, and the RF output is the BNC at the right.

Here are the schematics:

(Click on image to enlarge)

(Click on image to enlarge)
Notes on the Design:

Page 1:

This page contains the MOSFET Amplifier and its driving circuitry.

The amplifier consists of a pair of IRF530 MOSFETs in a push-pull configuration that drive a tank circuit consisting of transformer T1 and parallel capacitors C7 and C10. Why IRF530 MOSFETs? They were in my junk box!

These MOSFETs are rated at 100 volts max VDSS and have an RDS(on) of about 0.18 Ω (the latter depends upon which manufacturer's datasheet you look at).

The tank transformer, T1, consists of two windings, 5 turns each, with the secondary winding wound inside the primary winding (the windings are concentric). Total coil length is about 2.75", and the inner-diameter of the outer coil is about 1.5". After I wound T1 I discovered that its inductance measured to be around 570 nH. I'd been shooting for about 400 nH, but the difference isn't a big deal -- 570 nH just lowers the overall Q a bit (from a simulated Q (with 400 nH) of 5 to an actual Q of 3.6 at 3.87 MHz with a 50 ohm load). (See note later in this posting regarding measuring inductance of an unknown inductor).

C7, which, in combination with C10, forms the resonant tank capacitance, is actually six 510 pf ceramic capacitors (low ESR caps from American Technical Ceramics (their 700B series)). C10 is an air variable (20-420 pf) from my junk box, and it gives me a tuning range of approximately 3.78 MHz to 4.03 MHz.

Peak voltage across these tank components is on the order of 80 volts or so, so there's no reason for high-voltage parts. However, current through the inductor and capacitors is on the order of 3 to 5 amps RMS (per my SPICE simulations), so low-ESR components are highly recommended.

The MOSFET Drains are fed via 18 uH inductors L1 and L2. I had wanted to use higher inductance, but I didn't have anything in the junk box that was suitable (high inductance and high self-resonant frequency (S.R.F.)). However, I did have a couple of J.W. Miller 5252 inductors -- these are 125 uH inductors, but their self-resonant frequency is only about 2.5 MHz. I removed the top two winding layers (of three total layers) to give me an inductance of 18 uH and an S.R.F. of about 48 MHz.

I decided that the simplest way to drive the PA MOSFETs would be with MOSFET drivers. I chose IXDD414 MOSFET drivers (note: these are obsolete parts, but I found mine on Ebay). They drive the MOSFETs via 1-ohm resistors, which seemed to reduce ringing (but this observation really should be reconfirmed -- take it with a grain of salt).

To drive the IXDD414 Drivers I use two XOR gates to generate, from the VFO signal, two signals of the same frequency but 180 degrees out of phase with each other. One of the XOR gates inverts the VFO signal, while the other passes it through uninverted. Both XOR gates are on the same die, which should minimize the differential delay between the two signals.

The VFO signal is AC-coupled to an input on each of these two XOR gates, and two potentiometers provide variable DC offsets to each of these same two inputs so that the duty-cycle (i.e. symmetry) of each XOR output can be independently adjusted.

(Note: For testing I drove the XOR gates with an HP 8640B signal generator, set to +10 dBm. At this level, this generator provides a nice, very low distortion sine-wave with about a 4 Vpp amplitude (rather than 2 Vpp, which you'd expect at +10 dBm, because the 8640B is now terminated in a high impedance, rather than 50 ohms)).

The final bit of circuit on this page of the schematic, Q1 (a P-channel MOSFET), ramps the DC voltage feeding the IRF520 Drains up and down when the amplifier is turned on and off, thus providing a soft, rather than hard, transition to the output RF envelope. (I tried using the enable pins on the IXDD414 ICs in lieu of adding this MOSFET, but I found there were voltage spikes on the Drains of the IRF530 MOSFETs exceeding their VDSS when I transitioned these Drivers ON using their enable pins).

Page 2:

This page contains the voltage regulators and control circuitry.

An LM2576 switching regulator provides the +12VDC power for the IXD414 MOSFET Drivers. These two drivers require about 0.4 - 0.5 amps of current, total. A 12V linear regulator would have had to dissipate about 5 to 6 watts of power, which is why I chose to go with a more efficient switching regulator.

The values for the switching-regulator's components are straight out of the LM2576 datasheet. Note that this datasheet specifies a 1000uH inductor for the 12V regulator when the input voltage is around 26V and the load current around 0.4 Amps. Pulse Electronics has a series of "50 KHz Inductors" (available through Digikey) that are recommended for LM2576 applications. I used the PE-53120, which is a 1000 uH inductor.

A 7805 5-volt linear regulator provides 5VDC for the digital logic.

This amplifier is designed to be keyed by my 813 AM transmitter. Because I want the VFO to be inaudible in my receiver when I'm not transmitting, I need some way to disable it (or move it off frequency) when I'm not transmitting. Also, I want the VFO to be enabled and generating its signal before I apply power to the MOSFET Drains and to go OFF after I remove power from the MOSFET Drains when I'm done transmitting, so that the VFO is stable at all times while power is being applied to the MOSFETs. In other words, I want to "nest" the MOSFETs' ON/OFF cycle within the VFO's enable/disable cycle.

Although I could use the 813 Transmitter's sequencer to nest the MOSFET Power ON/OFF within the VFO Enable/Disable, for ease-of-testing I decided to incorporate a sequencer into this design to allow me to test this amplifier as a stand-alone unit. This new sequencer is also based upon the W2DRZ design. In the future, when I incorporate this circuit into the 813 AM Transmitter, I will decide if I should use the 813 AM Transmitter's sequencer in lieu of this one.

This sequencer runs at a 50 Hz clock rate because I want it to run faster than the sequencer in my 813 Transmitter (which I've set to run at roughly a 10 Hz clock rate).

I plan to drive this amplifier with an N3ZI DDS Module, which I would like to disable when I'm not transmitting so that it doesn't interfere with reception. There are a couple of ways that this might be done. One is to shift the VFO to a completely different frequency (using the DDS Module's "VFO B/A" input).

Moving the VFO off frequency when not transmitting would prevent Receive interference, but it might be also useful to shut off the VFO when transmitting so that the MOSFET Drivers (which are driven by the VFO via the XOR gates) aren't consuming power from the 12V supply. There are several ways in which one might do this:

One way might be to "lift" (via an open-collector/drain driver) the ground-end of R1, the 6.8K resistor attached to the AD9834's FS ADJUST pin (pin 1), when not transmitting. Per the AD9834 datasheet:

(FSADJUST = 1.15V nominal, and
RSET is R1 in the N3ZI DDS2 VFO schematic)

Thus, raising the resistance of R1 during Receive should reduce IOUT to near zero.

Another possible way to disable the VFO might be to simply short the IOUT output from the AD9834's IOUT to ground. This is a current-source output, of which the DDS chip has two (IOUTB is the second one), and the datasheet states that IOUTB can be shorted to ground if not in use, so I would think that one could also short-out the first output, too, to disable the DDS (both are rated at the same output current). But is this advisable? I can't say. Also, the current at IOUT would still be generated and thus sourced out the IOUT pin, and so any "non-zero area" current-loop formed by the "shorting" components and IOUT's signal path could still create some amount of interfering RF emissions on the receive frequency.

And perhaps the easiest way would be to simply take the IXDD414s' EN pins (pin 5) to ground at the same time that the VFO frequency is shifted (i.e. VFO disabled).

There are some signals on this schematic page, such as MUTE VFO, that could be used for just this purpose (e.g. tie MUTE VFO to the U8.5 / U9.5 node). I'll determine which route is best when I incorporate the N3ZI DDS module.

Notes on Construction:

I built the circuit on a piece of 6.5" x 4.5" scrap single-sided copper-clad FR4 circuit board. The copper plane on this board is used as the circuit ground. I cut up pieces of double-sided FR4 PCB material to use as mounting pads and power busses (one side of each is soldered to the copper "ground plane" on the main board).

Regarding the MOSFETs and their MOSFET drivers (and any other components with high slew-rate signals), it's important to minimize parasitic inductance, so keep leads as short as possible.

Caps used for power-supply bypassing (e.g. C23-C26, C29 and C30) should have very high self-resonant frequencies, and they should be mounted as close to the IXDD414s power pins (and ground) as possible to minimize unwanted inductance from their leads.

It's a good idea to try to ensure that each Drain of the IRF530 MOSFETs sees approximately the same amount of capacitance-to-ground from the wiring and other sources -- my SPICE simulations showed that unequal amounts of capacitance-to-ground for the two MOSFETs results in unequal voltage peaks, with respect to ground, at the Drains of the MOSFETs.

The IRF530 MOSFETs are attached to a heatsink consisting of a copper buss-bar that's 1" x 4.75" x 0.125". This heatsink is electrically attached to the circuit ground with copper tape and also a small angle bracket that mechanically holds the heatsink to the circuit board.

The transformer T1 is constructed of rectangular 3/16" x 1/16" enameled copper magnet wire (this is the same wire used by Taniguchi, Potter, Rutledge in their 200 W Power Amplifier which appeared in the Jan/Feb 2004 issue of QEX). It consists of two windings, 5 turns each. Total length is about 2.75", and the inner-diameter of the outer coil is about 1.5". The secondary-winding is closely wound inside the primary winding (to minimize leakage-inductance), and I covered one of the windings with Kapton tape when I found that the wire's enamel was sometimes cracking as I bent it, and I was concerned that the two windings might short-out to each other.

The LM2576 datasheet has useful tips for layout and interconnection of components.

Adjustments and Tuning...

There are three adjustments to make: The two Symmetry potentiometers, R3 and R6, set the duty-cycle of the outputs of the two XOR gates, and the Tune variable capacitor, C10, in the output Tank Circuit allows the Tank's resonant frequency to be tuned roughly 250 KHz.

Initial Setup:
  • While not transmitting (PTT IN is still high), I first set the two pots, R3 and R6, to midway in their adjustment range. While monitoring the XOR outputs with a scope, I then I tweak the two potentiometers so that the outputs of the XOR gates are each at (or close to) a 50% duty-cycle.
  • I then take PTT IN low to enable the transmitter. While monitoring the two Drain waveforms on an oscilloscope, I tweak the two pots to try to minimize the "ringing" on the MOSFET Drain signals. (See note below regarding how to accurately probe the Drains). Note: The final setting of each pot seems to correspond to a duty-cycle very close to 50% for each XOR output.
  • Then I adjust the frequency of the VFO for minimum Drain current (using a voltmeter across the 0.1 Ω resistor, R12, to monitor DC Drain current).
  • I again tweak the pot adjustments to again minimize ringing on the two Drain waveforms. (If you have a Spectrum Analyzer, you can also monitor the spectrum (out to, say, 100 MHz) and adjust the pots to minimize the higher-frequency spikes).

The result should look something like this:

(Click on image to enlarge)

Once these adjustments have been made, I find that I can keep the pot settings fixed and only change C10 when I move to a different frequency. (When moving to a different frequency, you can try retuning C10 for minimum Drain current, but I personally find that approach only gets me into the ballpark. The approach I follow is described in more detail just a bit later in this section.

Per my measurements, the efficiency of the MOSFET amplifier itself is around 90% (this number should be taken with a grain of salt, as it depends a great deal upon the accuracy of your watt-meter as well as DC current and voltage measurements!), and efficiency drops to about 86% at about 100 KHz of either side of the frequency to which C10 is tuned to. However, ringing is starting to look pretty severe at this point, and so I'd recommend changing the VFO by no more than, say, +/- 50 KHz before retuning C10.

When misadjusted, the Drain waveforms can look like the following image (or much worse!). Note that this is ringing on the waveform, not oscillation.

(Click on image to enlarge)

When changing frequency, I only adjust the capacitor, C10. The two pots I leave alone after their initial adjustment (see above).

When tuning to a new frequency, my procedure to adjust C10 is a bit iterative. You can try to adjust it for minimum Drain current, but I find that this approach doesn't always work. Instead, I do the following:
  • Rotate C10 to where you think it should be, approximately, for the frequency you'll be using.
  • Tune the VFO for minimum Drain current.
  • If the frequency of the VFO, after tuning, isn't close enough to where you'd like to be, tweak C10 a bit and repeat.
This approach seems to work for me.

Knocking Down the High-Frequency Junk

The output of the Class E/F amplifier is fairly dirty with high-frequency trash from 1) Harmonics (and ringing) on the MOSFET Drain waveforms, and 2) pickup of harmonics from the XOR gates and MOSFET Drivers.

Here's the spectrum of the Amplifier's output prior to adding an external filter.:

(Click on image to enlarge)

(Measurements made through a 30 dB Bird attenuator. The signal at the far left is the fundamental (at about 3.8 MHz), and the next signal (very low level) is the second harmonic.)

The above chart shows spurs out to 100 MHz. In reality they extend well past this frequency. In an attempt to reduce them, I first tried a 5-element Chebychev low-pass filter from the tables in the ARRL Handbook (Fig. 12-19, #7, for fco of 4.5 MHz, which results in values of 620 pf for the input and output caps, 1200 pf for the middle cap, and 2.39 uH for the two inductors).

But when I tried using this filter, I had to crank up my power-supply to about 30 volts to get the same amount of RF power output. So I nixed this filter (The peak Drain-Source voltage for the IRF530 MOSFETs was at its limit).

Instead, I decided to incorporate a simple diplexer, similar (in topology) to the one described in the Part 2 article of the High-Efficiency Class-E Power Amplifiers. . To keep the design simple, I designed for a Q of 1, which means that the inductors and the capacitors are the same in both "halves" of the diplexer. Here's its schematic:

(Click on image to enlarge)
The caps are dipped silver-mica (300V rating), and the inductors were wound with 26 gauge enameled wire. I'm using a BNC-mounted Tek 50 ohm, 1/2 watt termination to terminate the parallel L-C branch of the diplexer. After about 1/2 hour of "key-down" operation, this termination gets a little bit warm.

With this filter, the PA requires a DC Power Source of about 25.7 VDC to generate 39 watts RF Power out.

And here's the resulting spectrum:

(Click on image to enlarge)

Because of its low Q, the Diplexer doesn't do much to knock down harmonics that are near the fundamental, such as the 2nd and 3rd harmonics. But because of the symmetrical output of a push/pull amplifier topology, the 2nd harmonic is already quite far down (when the Symmetry pots are properly adjusted), and the 3rd harmonic is now more than 40 dB below the fundamental.

One advantage to a diplexer implementation is that it presents a near 50 ohm load to all frequencies (assuming that the external load presented to the series L-C filter is 50 ohms at its resonant frequency). This can help stabilize an amplifier that might otherwise be unstable when presented with off-frequency unknown impedances.

Accurately Probing the MOSFET Drain Voltage Waveforms

If you try measuring Drain voltage waveforms with a standard scope probe and its ground lead, you are not going to get an accurate picture of what the waveform actually looks like. Instead, you are very likely to see all kinds of junk on the signal. This "junk" really isn't on the signal -- it's radiated noise picked up by the inductive "loop" formed by the scope probe and its ground lead.

To get an accurate picture of how the signal really looks, you need to minimize the capture area of this loop. The best way to do this is to keep the ground "lead" as short as possible, and connect ground to the probe as close to the probe tip (where the signal being probed is) as possible.

For this purpose I adapted a Tektronix PCB to probe-tip adapter (Tek p/n 131-4244-00, made for probes such as the P6139A). I soldered two pins of the four-pin "ground" shell to the PCB copper-clad upon which I'd built the amplifier (the other two pins are in the air, as you can see in the photo below), and the socket for the probe tip I soldered to the Drain buss for one of the MOSFETs. The other MOSFET has the same setup so that I can monitor both Drains simultaneously.

(Click on image to enlarge)

(There's a useful app note from Analog Devices here. Although it discusses probing high-speed signals, its techniques are quite applicable to this circuit, too.)

Other Notes and Thoughts:

1. Measuring Inductance or Self-Resonant Frequency of an inductor:

Here's the technique I use. There might be better approaches, but this one worked for me...

(Click on image to enlarge)
2. Tank Capacitors:

Per my SPICE simulations, the tank circuit has large currents -- on the order of 3 to 5 Amps RMS. So you want the tank capacitance to have a very low ESR to minimize unwanted power dissipation.

For my tank capacitance, I used six 510 pf caps in parallel. The capacitors are manufactured by American Technical Ceramics, and are from their 700B series. The ESR of their 510 pf capacitor is in the range of 0.04 - 0.05 Ω. If we assume 0.5A of current passes through each cap (ball-parking 3A RMS total current through six caps), the power dissipation in each is then on the order of 0.01 watts. Not too bad!

(In hindsight, though, I probably should have used their 470 pf caps. The 510 pf caps have a working voltage of 100 volts, which is a bit too close to the voltage they're actually seeing in this circuit (see scope images above of the Drain waveforms). The 470 pf caps, on the other hand, have a working voltage of 200 V, which gives a nice margin. If I can get these caps in, I'll replace the 510 pf caps.)

3. IRF530 MOSFETs: These have a max VDSS of 100V. I'd like to have a bit more margin (per the discussion above regarding the 510 pF capacitors), but that's what was in the junk box when I looked for suitable parts. We'll see if there's any issue with reliability.

4. Some useful formulas:
  • For a resonant circuit: L = 1 / [ (2*π*f)2 * C ], or C = 1 / [ (2*π*f)2 * L ]
  • For a series RLC circuit, Q = (1/R) * √L/C, which, when combined with either of the two equations above, gives us: Q = |X/R|.
  • For a parallel RLC circuit, Q = (R) * √C/L, which, when combined with either of the two equations above, gives us: Q = |R/X|.
  • Note that when Q = 1, R = |X| for both the series and parallel RLC circuits.
5. 24V vs. 12V Power Supplies:

This design could be run from 12V (e.g. 13.4 VDC) rather than 24V (actually 26V) by changing the design of T1 to transform the 50 ohm load to a lower resistance across MOSFET Drains. This approach has two advantages: 1) Lowers the peak-voltage across the Tank components and at the Drains of the MOSFETs, and 2) Eliminates the need for the 12V switching regulator.

However, with the 24V supply, I can adjust the supply's output voltage (typically +/- 10%) to vary RF Output Power independently of the 12V supply (in case there are other radios running on the same 12V supply that might depend upon that voltage being fixed). Also, use of a 24V supply means that the transformer T1 for this application has a turns-ratio of 1:1, which (in my mind) simplifies its design. It would need to be on the order of 1:4 for a 12V application.

6. Transformer T1:

T1 consists of two concentric solenoid coils, air-wound with thick wire to minimize losses. It's possible that this transformer could be wound on toroidal or balun forms instead, using smaller gauge wire than the very large rectangular magnet wire that I used. It would be interesting to see what the effect of such a transformer would be on overall efficiency. Perhaps someday...

7. RF Power and Efficiency versus Power Supply DCV:

(Click on image to enlarge)
  • DC Voltage measured at the Q1 side of L1 and L2.
  • The burbles in the efficiency curve are probably due to measurement errors on my part.




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Class E Amplifiers:

Class E/F Amplifiers:


1. I could have easily have made a mistake, so please regard (and use) this design accordingly.

Thursday, January 27, 2011

Modeling Class E/F RF Amplifiers, Part 2

[Part 1 can be found here]

In Part 1 I evaluated a Class E/F amplifier using a center-tapped transformer to supply power to the drains of the two active devices.

DC power can also be fed to the drains of the two MOSFETs via two inductors, thus simplifying the transformer because it no longer needs to be center-tapped. I was curious how such a circuit compared (in performance) to the circuit described in Part 1.

Here's the SPICE model (using Linear Technology's free SPICE program: LTSpice):

(Click on image to enlarge)

Regarding the model:

1. C4, at 1 Farad, provides a "stiff" AC ground for simulation purposes so that there's no voltage fluctuation at the R4, C4, L1, L2 node.

2. L1 and L2 provide a high-impedance feed for DC power to the "Drains" of the MOSFETs. I chose these to be (initially) 25 uH.

3. The MOSFETs are modeled with voltage-controlled switches. Their Ron is set via external resistors to be 0.15 Ω (plus 0.01 Ω within the Switch model).

4. 500 pf capacitors mimic the MOSFETs' Coss (per the IRF 530 datasheet). Note that these capacitors are not voltage dependent.

5. Refer to Part 1 for more detail on selecting the Transformer inductance of 400 nH.

6. C3 was arrived at by trial-and-error (after initially setting its value to 3.655 nF per Part 1) by adjusting its value so that the voltage waveform at node "Va" is zero when the current waveform (through R1) is non-zero.

(Click on image to enlarge)

When adjust the value of C3 (or the transformer's inductance), the current and voltage waveforms maintain the same relationship to C3's value (or to the transformer's inductance) as was described in Part 1. Refer to the image below.

(Click on image to enlarge)

Lowering RMS current through the switches:

I thought I'd see if I could lower power dissipation in the switching devices by lowering their RMS current (see Part 1 for more discussion on this technique). By lowering the value of inductance of L1 and L2, I could replicate current waveforms through the switching devices that look as though the amplifier is now a a "Class E/F2,odd" amplifier, but, when I made my measurements using the tools in LTSpice, there was really only minimal effect (if any) in power dissipation.

Here's how the waveforms look with L1 and L2 reduced to 800 nH. As the table following this image shows, although the current-waveform changes significantly, there isn't much of a difference in switching-device power-dissipation (as measured across R1 and R2).

(Click on image to enlarge)

I used the LTSpice measurement functions to measure power and RMS current at different points in the circuit (for various values of L1, L2), and these measurements have been tabulated below.

(Click on image to enlarge)

Some observations from this table:
  • I really cannot see much change in R1's power dissipation as L1, L2 are varied. That is, the differences are small, and perhaps are within the tolerance of simulation errors.
  • Also, there's not much change in either Output Power (Pload) or efficiency for the range of values of L1 and L2 shown in the table. Therefore, a L1, L2 values in the range of, say, 25 uH - 100 uH, might be the simplest approach for my application.
  • As L1, L2 are decreased, C3 must be increased to compensate for their effect on the time-relationship of the voltage and current waveforms. However, an increase in the value of C3 increases the current through C3 (because voltage across the transformer is essentially constant, and we decrease C3's reactive impedance when we increase its value). Therefore, due to its internal ESR, C3 will dissipate more power when L1,L2 are reduced.
  • As the values of L1 and L2 is increased, it takes longer for the simulation waveforms to ramp up to their final values.
From the minimal change in R1 dissipation, and from the gross changes in C3 current (and thus, potentially, its power dissipation), it really doesn't make much sense (in my application) to attempt to "tune" L1 and L2 to minimize power dissipation in the switching devices by minimizing their RMS currents.

It's possible, though, that in applications in which higher currents are present, some benefit might be achieved by "tuning" L1 and L2. However, the simulations don't bear this out in my application, and there seems to be little benefit.

Overall, the power-out from this circuit topology is comparable to that of the center-tapped transformer topology described in Part 1. So, for my application, either circuit should do the job, and it'll just be a matter of determining which one is easiest to build.

Modeling with the IRF530 MOSFET

Actual MOSFETs can be simulated via LTSpice's "nmos" model, within which one can retrieve the SPICE parameters for a number of different MOSFETs, including the IRF530. (Note: these devices are not alphabetized in the "Pick New MOSFET" table.)

Below is a circuit with IRF530 MOSFETs substituting for the original voltage-controlled switches. The final value of C3, as well as the AC source's amplitude and offset voltage (V2), were arrived at by trial-and-error. Also, two AC sources are used (the second with an offset of 180 degrees), because it seemed like an easy way to provide two sine-wave sources that were 180 degrees out of phase but with the same DC offset.

(Click on image to enlarge)

There are several differences between this circuit model and the original one with the voltage-controlled switches:
  1. The Sine Wave sources have an amplitude of 10 Vpeak and a DC offset of 5V (to bias the IRF530's near their turn-on point). This gives peak gate voltages of +15/-5 Volts (note that the max rating of the IRF530's gate voltage (VGS) is +/- 20V).
  2. C3 is now 3.69 nF.

Here is the Drain Voltage versus Source Current for one of the IRF530 MOSFETs:

(Click on image to enlarge)

Note: Source current is shown, rather than Drain current, because the Drain pin has quite a bit of current flowing through it even when the MOSFET is OFF. This current at the Drain pin is not dissipative current, though (that is, it isn't being dissipated as I2 * R heat through RDS(on). Instead, it's current passing through the Gate-Drain capacitance and out the Gate pin (LTSpice plots verify that I(drain) - I(gate) = I(source)).

Here are some of the currents and powers (and overall efficiency) measured via LTSpice.
  • RF Power Out: 48.2 watts
  • DC Power In: 52.0 watts
  • Efficiency: η = 48.2/52.0 = 93%
  • IL1 = 1.14 ARMS
  • IC3 = 4.5 ARMS
  • IL3 = 5.2 ARMS
Note the high currents in C3 and L3. Care should be taken to use low-ESR devices!


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Class E Amplifiers:

Class E/F Amplifiers:


1. These simulations are for educational purposes only.

2. I could have easily have made a mistake, so please view (and use) these simulations accordingly.

3. And a final caveat regarding SPICE modeling. Modeling results should always be taken with a bit of caution, for the ability of SPICE to mimic actual circuit behavior depends in large part on how accurately a circuit and its components have been modeled. Factors such as parasitic components and circuit non-linearities can all cause modeled SPICE performance to diverge from actual performance. SPICE can provide valuable insights into circuit operation, but a bit of skepticism, too, should be applied when evaluating results.

Wednesday, January 26, 2011

Modeling Class E/F RF Amplifiers, Part 1

[Part 2 can be found here.]

I've recently been thinking of replacing the Johnson Ranger which drives my 813 AM transmitter with something more modern and which consumes less power -- a homebrew, solid-state unit which would replace the Ranger's RF driver and Speech Amplifier.

The Ranger drives my 813 AM transmitter with 36-37 watts of RF Power(SWR is 1.27:1, by the way). I have a DDS VFO module that I'd like to use as the frequency-control of my Ranger-replacement, but its output is probably on the order of milliwatts (not yet measured), so I'll need to boost it with (probably) several stages of RF amplification.

With that thought in mind, I started researching possible amplifier circuits that might provide the required 40 - 50 watts of RF power on 75 meters.

I'd like to maximize efficiency of the PA, and of course Class-C Amplifier topologies immediately leapt to mind. But while researching designs, I came across the Class-E mode of amplification which promised improved efficiencies over Class C. This looked very worthwhile, and the design procedures for such amplifiers seem to be well established.

However, as I searched the literature, I stumbled across an interesting QEX article ("A 200 W Power Amplifier", in the Jan/Feb 2004 issue) describing a Class E/F amplifier for 40 meters. The Class E/F topology (being push/pull) offers benefits over Class E, such as:
  • Lowers the required Vdc power supply voltage for the same power out.
  • Lowers Vds across the MOSFETs for the same power out.
  • Improves harmonic suppression.
Further investigation was needed!

Unfortunately, design methodology for the Class E/F amplifiers doesn't seem to be at the same state as that of Class E amplifiers. Not letting that deter me, I figured SPICE modeling of these amplifiers would allow me to play around with circuit parameters and component values, and I would (hopefully) gain some insight into their operation and possible component values for my application. (By the way, there's a free SPICE program available via the Linear Technology website).

Building a SPICE Model of a Class E/F amplifier:

Below is my SPICE model for a Class E/Fodd amplifier. It's topology is based upon the amplifier circuit described in the 7 MHz, 1.1 KW demonstration amplifier by Kee, Aoki, and Rutledge). My goal was to design a PA for 75 meters (3.87 MHz, typical frequency) and output power (at the 50 Ω load resistor) on the order of 40-60 watts.

(Click on image to enlarge)
(Note: Comments are in BLUE, SPICE directives are in BLACK).

How did I arrive at the component values in the above circuit? Let's look at my procedure:

First, my givens: Rload = 50 Ω. Desired power out: 50 watts.

Next, I wanted to select a power-supply voltage (Vdc) that would:
  1. Allow me to use a 1:1 impedance transformation from load to the differential connection across the PA MOSFET drains.
  2. Not be too high of a voltage so that I could use 100V (VDSS) MOSFETs that are in my junk-box (e.g. IRF 530) .
  3. Yet be high enough to minimize current through the MOSFETs and the resultant "i2 R" power loss through their RDS(on) resistance.
Per my design goal of an amplifier that delivers 50 watts into a 50 Ω load, this means that the voltage across the 50 Ω load is 70.7 volts peak (141.4 Vpp or 50 volts RMS).

And per my goal of not requiring impedance transformation (either from high-to-low or low-to-high impedance) from the load to the MOSFETs' drains, I'm using a 1:1 transformer to present the 50 Ω load resistor as 50 Ω to the PA MOSFETs' drains (this load appears differentially between the two drains).

From the Class E/F literature, the peak voltage across the drain of each MOSFET is ≈ π*Vdc, where Vdc is the power-supply voltage (refer to equations 37 & 38 in "The Class E/F Family of ZVS Switching Amplifiers", for example). So, in my case of an untransformed (i.e. 1:1) 50 Ω load, then the peak value of the voltage at the drain of either MOSFET is the same as the peak value across the 50 Ω load resistor. In other words, Vds(peak) = Vload(peak), where the load is R3 in the circuit model above. Using this equality, we can derive the following equation:

Vdc ≈ [ √(Pload * Rload) ] / [ π * (√2) / 2]

Where Pload = power delivered to Rload (R3), and therefore Pload = [ (√2 / 2)*π*Vdc]2 / Rload, using our definition of Vpeak = π*Vdc.

In this case in which Power = 50 watts and Rload = 50 Ω, Vdc calculates to be 22.5 volts. (Note: I'm using 22.8 volts for my modeling, which is the lower-limit of the output voltage adjustment of some off-the-shelf 24 volt switching supplies), and Vds (peak) across either MOSFET is π*Vdc, or 71.6 volts peak. The IRF 530 MOSFET has a rated VDSS of 100 volts, so there's almost 30 volts of margin.

OK, now it's time to calculate the inductance that we'll need between the drains of the two MOSFETs. This is the inductance of the primary of the center-tapped 1:1 transformer. Because the transformer is 1:1, the inductance of the primary is the same as the inductance of the secondary (same number of turns in each). To determine the inductance of the primary, let's first assume it has a loaded Q of 5. (I'm actually going to use 5.1). Why 5? In fact, some of the Class E/F amplifiers in the literature use a Q of around 3 or even less. I'd like to keep Q sort of high so that harmonic suppression isn't too compromised, but this may need adjusting if/when I actually build the circuit.

OK -- the inductance of the transformer's primary is loaded by Rload (R3), reflected through the transformer from the secondary. Thus, because the transformer is 1:1, this 50 Ω load appears as 50 Ω across the primary, and it is this 50 Ω that "loads" the Q.

Because L and R are in parallel, we know that:

Q = |R / XL|

In this case Q is actually Qloaded, and so we can rewrite this equation to give us L:

L = R/(2 * π * f * Qloaded),

which, in our example, gives us the following:

L = 50/(2*3.14*3.87e6*5.1)
= 400 nH

Now let's use this value to model our transformer...

To create a center-tapped transformer in LTSpice, we need to use three coupled-inductors. Two of these inductors represent the turns on either side of the primary center-tap (and thus each has half the number of turns of the secondary, given that the transformer is 1:1), and the third inductor is the secondary.

We know that the primary should have an inductance of 400 nH. Therefore, the secondary, because it has the same number of turns as the primary, will also have an inductance of 400 nH.

The two inductors representing the two halves of the primary each has half the number of turns as the secondary. Therefore each has 1/4 of the inductance of the secondary (inductance has a turns-squared relationship). So we specify each of these two inductors, in SPICE, to have 100 nH inductance. This gives us a 1:1 center-tapped transformer. (Refer to LTSpice "Help" for more information on Transformer modeling, and an example of a model for a 1:3 transformer).

Let's give these inductors some series resistance so that they represent "real" rather than "ideal" components -- that is, they have some amount (albeit small) of series resistance. The two inductors in the primary, because they're coupled, represent 400 nH overall inductance. Let's assume an unloaded Q of 150 for this overall inductance. Because this is a series R-L configuration, we use a slightly different formula for Q:

Q = |XL / R|

Solving for R:

R = 2 * π * f * L / Q
= 2*3.14*3.87e6*400e-9/150
= 0.065 Ω

I've rounded this down to 0.06 Ω, and I'm splitting it into two 0.03 Ω resistors which I place in series with either side of the transformer's primary.

(Note: in the past (and perhaps still) SPICE programs sometimes had problems converging upon a solution if one specified only ideal components. From habit I tend to throw in small values of resistance in series with an ideal component, such as the 0.06 Ω in series with the inductor(s) described above, with the hope that they'll nip such problems in the bud.)

What should be the value of the resonating capacitor (C3)? Unfortunately, I couldn't find an equation for calculating this value. All I know is that the overall impedance of the parallel L-C circuit represented by the transformer primary and C3 (in the circuit above) should be slightly inductive (per Class E/F references). This means that, because the circuit is a parallel-resonant circuit, the resonant frequency of the L-C combo should be slightly above the circuit's operating frequency.

But how far above should it be? I don't know, and I cannot find an equation to calculate it. [For further discussion of how one might calculate C3, please refer to Note 3 in the Notes section at the end of this posting].

So perhaps we should run some simulations and see if we can find it by trial and error...

But before I get to that, let me first fill in the remaining components in my SPICE circuit model:

I've set the dc-feed series inductor (L1) to an arbitrarily large value, in this case 10 uH (for no good reason, I chose 25 times 400 nH).

C4 is set to the humongous value of 1 Farad to provide a "stiff" AC ground. (At 1 uF, the value I'd originally set it to) there was some voltage fluctuation at the C4, L1, R4 node, and so I thought it better, for simulation purposes, to make the AC ground here as solid as possible).

I'm modeling the MOSFETs with (almost) ideal voltage-controlled switches (LTSpice's "SW" model). Because I'm not concerned (at the moment) with modeling the MOSFET inputs and drive circuit, I can define the inputs to be whatever is most convenient for me. Thus, I've set the switching thresholds of the SW model to 0 volts, and the switches are driven by a 1-volt amplitude sine-wave that has a 0 volt DC offset. Each switch is on for one-half of a full cycle, and neither switch is on at the same time.

The default SW model in LTSpice has an Ron of 1 Ω, which is much too large for our purposes. The IRF 530 MOSFET that I'd like to use has an RDS(on) of 0.15 Ω (depending upon which manufacturer's datasheet you look at). Although I could specify Ron in the SW model to be 0.15 Ω, I personally prefer to specify it as a separate component in series with each switch, and thus I also changed the SW model's Ron value from 1 Ω to an arbitrarily small value (in this case 0.01 Ω).

Similarly, I've placed the MOSFETs' Drain-Source Output Capacitance (Coss) across each series combination of 0.15 Ω and SW model. In the case of the IRF 530, Coss is 500 pf, which I've shown here in my circuit model.

So now we're back to C3. How do I determine its value? Let's use SPICE to find it by trial-and-error...

Let's start by assuming it resonates with 400 nH (the transformer's primary inductance) at our operating frequency of 3.87 MHz. This gives us a value for C3 of 4.22 nF.

Plugging this value into the model and running a simulation, it's quite apparent from the large current spikes that the voltage waveform at the "drain" of S1 is misaligned with respect to the current flowing through S1):

(Click on image to enlarge)

Playing around with the value of C3 and iterating to a solution, I found that a value of 3.655 nF for C3 gives a good result for the voltage and current waveforms. (This also results in a resonant frequency of 4.16 MHz).

(Click on image to enlarge)


Now that we've created our SPICE model of a Class E/F amplifier, let's do some experiments.

First, let's try decreasing and increasing C3 (and thus raising and lowering, respectively, the resonant frequency from the original value of 4.16 MHz).

Lowering the resonant frequency to 4.08 MHz by increasing C3 to 3.8 nF gives us this relationship between the voltage and current waveforms:

(Click on image to enlarge)

So if we see waveforms that looks like the above, we know that we need to decrease the capacitance of C3 to shift the voltage waveform to the left, relative to the current waveform.

Now let's raise the resonant frequency to 4.25 MHz by decreasing C3 to 3.5 nF:

(Click on image to enlarge)

And if we see waveforms that look like the above, we know we need to increase the capacitance of C3 to shift the voltage waveform to the right, relative to the current waveform.

Notice in the above images how the voltage waveform shifts with respect to the current waveform as we move the L-C network's resonant frequency up and down. Our goal is to adjust C3 so that we minimize the power dissipated within the MOSFETs (Vds is 0 volts when current is non-zero). This leads us to the following rule-of-thumb, as expressed in the image below:

(Click on image to enlarge)

Lowering RMS current through the switches:

Reduction of the RMS current through the switching devices can be accomplished by resonating L1 with the switch's Coss (C1 or C2) near the second harmonic of the operating frequency (refer to section "C" in the 7 MHz, 1.1KW Amp reference for more information). This type of configuration is known as a "Class E/F2,odd" amplifier.

Here's the resulting waveforms when L1 is changed from 10 uH to 500 nH.

(Note: C3 had to be changed from 3.655 nF to 3.798 nF to bring the voltage and current waveforms back into their proper time-relationship.)

(Click on image to enlarge)

A couple of points:

1. I played around with different values of L1 (modifying C3 each time to maintain the proper time relationship for the Voltage and Current waveforms) and measured, via LTSpice measurement functions, RMS current and power at different points in the circuit. Here's a table of my results:

(Click on image to enlarge)
Some observations from this table:
  • Current (RMS) through a switch (i.e. I(R1)) is minimized when L1 = 500 nH. BUT, the delta in power dissipation (from, say, the case in which L1 = 100 uH) is only about 0.02 watts.
  • Also, current through other devices increases as the value of L1 is decreased. There is no "sweet spot" for these other currents when L1 = 500 nH, and the other devices will dissipate more power (because of their higher currents) as the value of L1 is decreased to 500 nH.
  • Overall, there's not much change in either Output Power (Pload) or efficiency for the range of values of L1 shown. Therefore, using an L1 value in the range of, say, 10 uH - 100 uH might be the best approach for my application.
  • I can't explain why there's as much difference as there is when L1 = 240 nH.
  • As C3 is increased to compensate for a decrease in L1, C3's current increases. Therefore, due to its ESR, it will dissipate more power. (However, the delta in current when going from an inductance of 100uH to 500nH isn't too bad.)
  • As the value of L1 is increased, it takes longer for the simulation waveforms to ramp up to their final values.
2. L1, at 500 nH, resonates with the 500 pF value of C1 at about 10 MHz, which, although near to the second harmonic of 3.87 MHz, is actually a bit closer to the third harmonic. I don't know if there's a formula one can use to exactly calculate what L1 should be -- the literature seems to only state that the resonant frequency should be "near" the second harmonic. Iteration through trial-and error might be the only approach (at this time) for selecting an inductance for L1 to minimize switching-device power dissipation.

3. From these results, it's doubtful that, for my application, tuning L1 for minimum IRMS, through the switches would be worth the effort. However, this approach might prove more worthwhile in applications in which significantly more current flows through the switching devices.

Other notes:

1. An interesting observation I made while experimenting with the SPICE model is that, once you've set the phase (i.e. time) relationship of the switches' "drain" voltage and current waveforms, this relationship is independent of the DC supply voltage. That is, as you raise or lower Vdc, you will not change where the drain voltage is, in time, with respect to the drain current. In other words, you shouldn't need to "retune" the resonant circuit as you raise or lower Vdc. This also implies that you can change the power out simply by raising or lowering Vdc.

(This observed independence on Power Supply level probably depends, at least in part, on how independent the value of Coss is from the voltage across the Drain-to-Source of the MOSFET, which is something I don't know. Results might differ when using actual "real-world" components.)

2. Regarding the calculation of C3. After I finished my simulations I went back and reviewed some of the literature. There is a hint of how to determine C3 in the Cal Tech Thesis of Scott Kee (available as a PDF here). Refer to equation 7.18 and the discussion at the top of page 130.

The Thesis states, "it is apparent that the required fundamental frequency differential load is a resistance in parallel with an inductance having the same impedance at the fundamental frequency as the capacitance Cs does." Note that in our application Cs is the same as either C1 or C2 (Coss).

To me this statement means that we can consider the transformer inductance to consist of two "virtual" parallel inductors, one inductor resonating with C3 at the operating frequency, and the other inductor resonating with Coss, also at the operating frequency. In other words, the two inductors, as well as C3 and Coss, can all be considered a parallel circuit consisting of these four components (all in parallel), resonant at the operating frequency.

The 400 nH inductance is actually the combined inductance of the our two "virtual" parallel inductors. Let's look at the circuit configuration during the half of the cycle when S2 is closed: C2 is shorted and both one end of the transformer's inductance (400 nH) and C3 are grounded. This means that the 400 nH inductance, C1 (500 pf), and C3 (3.655 nF) are all in parallel. The equivalent capacitance is therefore 4.155 nF, which, in conjunction with 400 nH, gives us a resonant frequency of 3.90 MHz.

3.90 MHz is pretty close to (although not exactly at) my operating frequency of 3.87 MHz. Coincidence? Should C3, when it's paralleled with Coss, be calculated to resonate with the transformer's inductance at the operating frequency?

That is, should we use the equation:

F = 1/( 2 * π * √[ L(xfrmr) * (C3 + Coss) ] )

as a first-order approximation when deriving C3?


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Class E Amplifiers:

Class E/F Amplifiers:


1. These simulations are for educational purposes only.

2. I could have easily have made a mistake, so please view (and use) these simulations accordingly.

3. And a final caveat regarding SPICE modeling. Modeling results should always be taken with a bit of caution, for the ability of SPICE to mimic actual circuit behavior depends in large part on how accurately a circuit and its components have been modeled. Factors such as parasitic components and circuit non-linearities can all cause modeled SPICE performance to diverge from actual performance. SPICE can provide valuable insights into circuit operation, but a bit of skepticism, too, should be applied when evaluating results.