Wednesday, January 26, 2011

Modeling Class E/F RF Amplifiers, Part 1

[Part 2 can be found here.]

I've recently been thinking of replacing the Johnson Ranger which drives my 813 AM transmitter with something more modern and which consumes less power -- a homebrew, solid-state unit which would replace the Ranger's RF driver and Speech Amplifier.

The Ranger drives my 813 AM transmitter with 36-37 watts of RF Power(SWR is 1.27:1, by the way). I have a DDS VFO module that I'd like to use as the frequency-control of my Ranger-replacement, but its output is probably on the order of milliwatts (not yet measured), so I'll need to boost it with (probably) several stages of RF amplification.

With that thought in mind, I started researching possible amplifier circuits that might provide the required 40 - 50 watts of RF power on 75 meters.

I'd like to maximize efficiency of the PA, and of course Class-C Amplifier topologies immediately leapt to mind. But while researching designs, I came across the Class-E mode of amplification which promised improved efficiencies over Class C. This looked very worthwhile, and the design procedures for such amplifiers seem to be well established.

However, as I searched the literature, I stumbled across an interesting QEX article ("A 200 W Power Amplifier", in the Jan/Feb 2004 issue) describing a Class E/F amplifier for 40 meters. The Class E/F topology (being push/pull) offers benefits over Class E, such as:
  • Lowers the required Vdc power supply voltage for the same power out.
  • Lowers Vds across the MOSFETs for the same power out.
  • Improves harmonic suppression.
Further investigation was needed!

Unfortunately, design methodology for the Class E/F amplifiers doesn't seem to be at the same state as that of Class E amplifiers. Not letting that deter me, I figured SPICE modeling of these amplifiers would allow me to play around with circuit parameters and component values, and I would (hopefully) gain some insight into their operation and possible component values for my application. (By the way, there's a free SPICE program available via the Linear Technology website).

Building a SPICE Model of a Class E/F amplifier:

Below is my SPICE model for a Class E/Fodd amplifier. It's topology is based upon the amplifier circuit described in the 7 MHz, 1.1 KW demonstration amplifier by Kee, Aoki, and Rutledge). My goal was to design a PA for 75 meters (3.87 MHz, typical frequency) and output power (at the 50 Ω load resistor) on the order of 40-60 watts.

(Click on image to enlarge)
(Note: Comments are in BLUE, SPICE directives are in BLACK).

How did I arrive at the component values in the above circuit? Let's look at my procedure:

First, my givens: Rload = 50 Ω. Desired power out: 50 watts.

Next, I wanted to select a power-supply voltage (Vdc) that would:
  1. Allow me to use a 1:1 impedance transformation from load to the differential connection across the PA MOSFET drains.
  2. Not be too high of a voltage so that I could use 100V (VDSS) MOSFETs that are in my junk-box (e.g. IRF 530) .
  3. Yet be high enough to minimize current through the MOSFETs and the resultant "i2 R" power loss through their RDS(on) resistance.
Per my design goal of an amplifier that delivers 50 watts into a 50 Ω load, this means that the voltage across the 50 Ω load is 70.7 volts peak (141.4 Vpp or 50 volts RMS).

And per my goal of not requiring impedance transformation (either from high-to-low or low-to-high impedance) from the load to the MOSFETs' drains, I'm using a 1:1 transformer to present the 50 Ω load resistor as 50 Ω to the PA MOSFETs' drains (this load appears differentially between the two drains).

From the Class E/F literature, the peak voltage across the drain of each MOSFET is ≈ π*Vdc, where Vdc is the power-supply voltage (refer to equations 37 & 38 in "The Class E/F Family of ZVS Switching Amplifiers", for example). So, in my case of an untransformed (i.e. 1:1) 50 Ω load, then the peak value of the voltage at the drain of either MOSFET is the same as the peak value across the 50 Ω load resistor. In other words, Vds(peak) = Vload(peak), where the load is R3 in the circuit model above. Using this equality, we can derive the following equation:

Vdc ≈ [ √(Pload * Rload) ] / [ π * (√2) / 2]

Where Pload = power delivered to Rload (R3), and therefore Pload = [ (√2 / 2)*π*Vdc]2 / Rload, using our definition of Vpeak = π*Vdc.

In this case in which Power = 50 watts and Rload = 50 Ω, Vdc calculates to be 22.5 volts. (Note: I'm using 22.8 volts for my modeling, which is the lower-limit of the output voltage adjustment of some off-the-shelf 24 volt switching supplies), and Vds (peak) across either MOSFET is π*Vdc, or 71.6 volts peak. The IRF 530 MOSFET has a rated VDSS of 100 volts, so there's almost 30 volts of margin.

OK, now it's time to calculate the inductance that we'll need between the drains of the two MOSFETs. This is the inductance of the primary of the center-tapped 1:1 transformer. Because the transformer is 1:1, the inductance of the primary is the same as the inductance of the secondary (same number of turns in each). To determine the inductance of the primary, let's first assume it has a loaded Q of 5. (I'm actually going to use 5.1). Why 5? In fact, some of the Class E/F amplifiers in the literature use a Q of around 3 or even less. I'd like to keep Q sort of high so that harmonic suppression isn't too compromised, but this may need adjusting if/when I actually build the circuit.

OK -- the inductance of the transformer's primary is loaded by Rload (R3), reflected through the transformer from the secondary. Thus, because the transformer is 1:1, this 50 Ω load appears as 50 Ω across the primary, and it is this 50 Ω that "loads" the Q.

Because L and R are in parallel, we know that:

Q = |R / XL|

In this case Q is actually Qloaded, and so we can rewrite this equation to give us L:

L = R/(2 * π * f * Qloaded),

which, in our example, gives us the following:

L = 50/(2*3.14*3.87e6*5.1)
= 400 nH

Now let's use this value to model our transformer...

To create a center-tapped transformer in LTSpice, we need to use three coupled-inductors. Two of these inductors represent the turns on either side of the primary center-tap (and thus each has half the number of turns of the secondary, given that the transformer is 1:1), and the third inductor is the secondary.

We know that the primary should have an inductance of 400 nH. Therefore, the secondary, because it has the same number of turns as the primary, will also have an inductance of 400 nH.

The two inductors representing the two halves of the primary each has half the number of turns as the secondary. Therefore each has 1/4 of the inductance of the secondary (inductance has a turns-squared relationship). So we specify each of these two inductors, in SPICE, to have 100 nH inductance. This gives us a 1:1 center-tapped transformer. (Refer to LTSpice "Help" for more information on Transformer modeling, and an example of a model for a 1:3 transformer).

Let's give these inductors some series resistance so that they represent "real" rather than "ideal" components -- that is, they have some amount (albeit small) of series resistance. The two inductors in the primary, because they're coupled, represent 400 nH overall inductance. Let's assume an unloaded Q of 150 for this overall inductance. Because this is a series R-L configuration, we use a slightly different formula for Q:

Q = |XL / R|

Solving for R:

R = 2 * π * f * L / Q
= 2*3.14*3.87e6*400e-9/150
= 0.065 Ω

I've rounded this down to 0.06 Ω, and I'm splitting it into two 0.03 Ω resistors which I place in series with either side of the transformer's primary.

(Note: in the past (and perhaps still) SPICE programs sometimes had problems converging upon a solution if one specified only ideal components. From habit I tend to throw in small values of resistance in series with an ideal component, such as the 0.06 Ω in series with the inductor(s) described above, with the hope that they'll nip such problems in the bud.)

What should be the value of the resonating capacitor (C3)? Unfortunately, I couldn't find an equation for calculating this value. All I know is that the overall impedance of the parallel L-C circuit represented by the transformer primary and C3 (in the circuit above) should be slightly inductive (per Class E/F references). This means that, because the circuit is a parallel-resonant circuit, the resonant frequency of the L-C combo should be slightly above the circuit's operating frequency.

But how far above should it be? I don't know, and I cannot find an equation to calculate it. [For further discussion of how one might calculate C3, please refer to Note 3 in the Notes section at the end of this posting].

So perhaps we should run some simulations and see if we can find it by trial and error...

But before I get to that, let me first fill in the remaining components in my SPICE circuit model:

I've set the dc-feed series inductor (L1) to an arbitrarily large value, in this case 10 uH (for no good reason, I chose 25 times 400 nH).

C4 is set to the humongous value of 1 Farad to provide a "stiff" AC ground. (At 1 uF, the value I'd originally set it to) there was some voltage fluctuation at the C4, L1, R4 node, and so I thought it better, for simulation purposes, to make the AC ground here as solid as possible).

I'm modeling the MOSFETs with (almost) ideal voltage-controlled switches (LTSpice's "SW" model). Because I'm not concerned (at the moment) with modeling the MOSFET inputs and drive circuit, I can define the inputs to be whatever is most convenient for me. Thus, I've set the switching thresholds of the SW model to 0 volts, and the switches are driven by a 1-volt amplitude sine-wave that has a 0 volt DC offset. Each switch is on for one-half of a full cycle, and neither switch is on at the same time.

The default SW model in LTSpice has an Ron of 1 Ω, which is much too large for our purposes. The IRF 530 MOSFET that I'd like to use has an RDS(on) of 0.15 Ω (depending upon which manufacturer's datasheet you look at). Although I could specify Ron in the SW model to be 0.15 Ω, I personally prefer to specify it as a separate component in series with each switch, and thus I also changed the SW model's Ron value from 1 Ω to an arbitrarily small value (in this case 0.01 Ω).

Similarly, I've placed the MOSFETs' Drain-Source Output Capacitance (Coss) across each series combination of 0.15 Ω and SW model. In the case of the IRF 530, Coss is 500 pf, which I've shown here in my circuit model.

So now we're back to C3. How do I determine its value? Let's use SPICE to find it by trial-and-error...

Let's start by assuming it resonates with 400 nH (the transformer's primary inductance) at our operating frequency of 3.87 MHz. This gives us a value for C3 of 4.22 nF.

Plugging this value into the model and running a simulation, it's quite apparent from the large current spikes that the voltage waveform at the "drain" of S1 is misaligned with respect to the current flowing through S1):

(Click on image to enlarge)

Playing around with the value of C3 and iterating to a solution, I found that a value of 3.655 nF for C3 gives a good result for the voltage and current waveforms. (This also results in a resonant frequency of 4.16 MHz).

(Click on image to enlarge)


Now that we've created our SPICE model of a Class E/F amplifier, let's do some experiments.

First, let's try decreasing and increasing C3 (and thus raising and lowering, respectively, the resonant frequency from the original value of 4.16 MHz).

Lowering the resonant frequency to 4.08 MHz by increasing C3 to 3.8 nF gives us this relationship between the voltage and current waveforms:

(Click on image to enlarge)

So if we see waveforms that looks like the above, we know that we need to decrease the capacitance of C3 to shift the voltage waveform to the left, relative to the current waveform.

Now let's raise the resonant frequency to 4.25 MHz by decreasing C3 to 3.5 nF:

(Click on image to enlarge)

And if we see waveforms that look like the above, we know we need to increase the capacitance of C3 to shift the voltage waveform to the right, relative to the current waveform.

Notice in the above images how the voltage waveform shifts with respect to the current waveform as we move the L-C network's resonant frequency up and down. Our goal is to adjust C3 so that we minimize the power dissipated within the MOSFETs (Vds is 0 volts when current is non-zero). This leads us to the following rule-of-thumb, as expressed in the image below:

(Click on image to enlarge)

Lowering RMS current through the switches:

Reduction of the RMS current through the switching devices can be accomplished by resonating L1 with the switch's Coss (C1 or C2) near the second harmonic of the operating frequency (refer to section "C" in the 7 MHz, 1.1KW Amp reference for more information). This type of configuration is known as a "Class E/F2,odd" amplifier.

Here's the resulting waveforms when L1 is changed from 10 uH to 500 nH.

(Note: C3 had to be changed from 3.655 nF to 3.798 nF to bring the voltage and current waveforms back into their proper time-relationship.)

(Click on image to enlarge)

A couple of points:

1. I played around with different values of L1 (modifying C3 each time to maintain the proper time relationship for the Voltage and Current waveforms) and measured, via LTSpice measurement functions, RMS current and power at different points in the circuit. Here's a table of my results:

(Click on image to enlarge)
Some observations from this table:
  • Current (RMS) through a switch (i.e. I(R1)) is minimized when L1 = 500 nH. BUT, the delta in power dissipation (from, say, the case in which L1 = 100 uH) is only about 0.02 watts.
  • Also, current through other devices increases as the value of L1 is decreased. There is no "sweet spot" for these other currents when L1 = 500 nH, and the other devices will dissipate more power (because of their higher currents) as the value of L1 is decreased to 500 nH.
  • Overall, there's not much change in either Output Power (Pload) or efficiency for the range of values of L1 shown. Therefore, using an L1 value in the range of, say, 10 uH - 100 uH might be the best approach for my application.
  • I can't explain why there's as much difference as there is when L1 = 240 nH.
  • As C3 is increased to compensate for a decrease in L1, C3's current increases. Therefore, due to its ESR, it will dissipate more power. (However, the delta in current when going from an inductance of 100uH to 500nH isn't too bad.)
  • As the value of L1 is increased, it takes longer for the simulation waveforms to ramp up to their final values.
2. L1, at 500 nH, resonates with the 500 pF value of C1 at about 10 MHz, which, although near to the second harmonic of 3.87 MHz, is actually a bit closer to the third harmonic. I don't know if there's a formula one can use to exactly calculate what L1 should be -- the literature seems to only state that the resonant frequency should be "near" the second harmonic. Iteration through trial-and error might be the only approach (at this time) for selecting an inductance for L1 to minimize switching-device power dissipation.

3. From these results, it's doubtful that, for my application, tuning L1 for minimum IRMS, through the switches would be worth the effort. However, this approach might prove more worthwhile in applications in which significantly more current flows through the switching devices.

Other notes:

1. An interesting observation I made while experimenting with the SPICE model is that, once you've set the phase (i.e. time) relationship of the switches' "drain" voltage and current waveforms, this relationship is independent of the DC supply voltage. That is, as you raise or lower Vdc, you will not change where the drain voltage is, in time, with respect to the drain current. In other words, you shouldn't need to "retune" the resonant circuit as you raise or lower Vdc. This also implies that you can change the power out simply by raising or lowering Vdc.

(This observed independence on Power Supply level probably depends, at least in part, on how independent the value of Coss is from the voltage across the Drain-to-Source of the MOSFET, which is something I don't know. Results might differ when using actual "real-world" components.)

2. Regarding the calculation of C3. After I finished my simulations I went back and reviewed some of the literature. There is a hint of how to determine C3 in the Cal Tech Thesis of Scott Kee (available as a PDF here). Refer to equation 7.18 and the discussion at the top of page 130.

The Thesis states, "it is apparent that the required fundamental frequency differential load is a resistance in parallel with an inductance having the same impedance at the fundamental frequency as the capacitance Cs does." Note that in our application Cs is the same as either C1 or C2 (Coss).

To me this statement means that we can consider the transformer inductance to consist of two "virtual" parallel inductors, one inductor resonating with C3 at the operating frequency, and the other inductor resonating with Coss, also at the operating frequency. In other words, the two inductors, as well as C3 and Coss, can all be considered a parallel circuit consisting of these four components (all in parallel), resonant at the operating frequency.

The 400 nH inductance is actually the combined inductance of the our two "virtual" parallel inductors. Let's look at the circuit configuration during the half of the cycle when S2 is closed: C2 is shorted and both one end of the transformer's inductance (400 nH) and C3 are grounded. This means that the 400 nH inductance, C1 (500 pf), and C3 (3.655 nF) are all in parallel. The equivalent capacitance is therefore 4.155 nF, which, in conjunction with 400 nH, gives us a resonant frequency of 3.90 MHz.

3.90 MHz is pretty close to (although not exactly at) my operating frequency of 3.87 MHz. Coincidence? Should C3, when it's paralleled with Coss, be calculated to resonate with the transformer's inductance at the operating frequency?

That is, should we use the equation:

F = 1/( 2 * π * √[ L(xfrmr) * (C3 + Coss) ] )

as a first-order approximation when deriving C3?


  • Free Download of LTSpice here.
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Class E Amplifiers:

Class E/F Amplifiers:


1. These simulations are for educational purposes only.

2. I could have easily have made a mistake, so please view (and use) these simulations accordingly.

3. And a final caveat regarding SPICE modeling. Modeling results should always be taken with a bit of caution, for the ability of SPICE to mimic actual circuit behavior depends in large part on how accurately a circuit and its components have been modeled. Factors such as parasitic components and circuit non-linearities can all cause modeled SPICE performance to diverge from actual performance. SPICE can provide valuable insights into circuit operation, but a bit of skepticism, too, should be applied when evaluating results.


muhammad ali said...

can we draw schematics from simulated graphs using LTspice?

Jeff said...

Thanks for your question.

With LTSpice, you must first draw a schematic before you can generate graphs through simulation. Unfortunately, (to my knowledge) LTSpice does not let you reverse this process -- you cannot generate a schematic from a simulated graph.