Saturday, January 29, 2011

Building an 80-Meter Class E/F RF Amplifier...

After simulating on my computer an 80-Meter Class E/F amplifier (here and here), I decided to actually build one. Here it is:

(Click on image to enlarge)

With a 26V power supply, RF Power Out is about 40 watts. And efficiency of the MOSFET final is in the range of 85-95% (depending upon which power meter I use to measure RF power).

In the image above:
  • The two MOSFETs (IRF530, N-Channel) are mounted on the vertical copper plate at the upper-left.
  • The Tank circuit, including the transformer (5-turn air-wound coil) and a variable air capacitor (for tuning the tank) are at the upper-middle.
  • Control logic (and Symmetry adjustment potentiometers) are at the middle-left.
  • Two solenoid-style inductors (MOSFET Drain DC feeds) are lower middle.
  • A 12V switching voltage-regulator is at the lower-right (with the large toroidal inductor).
  • You can also see the two scope-probes attached to the MOSFET Drain busses, and the RF output is the BNC at the right.

Here are the schematics:

(Click on image to enlarge)

(Click on image to enlarge)
Notes on the Design:

Page 1:

This page contains the MOSFET Amplifier and its driving circuitry.

The amplifier consists of a pair of IRF530 MOSFETs in a push-pull configuration that drive a tank circuit consisting of transformer T1 and parallel capacitors C7 and C10. Why IRF530 MOSFETs? They were in my junk box!

These MOSFETs are rated at 100 volts max VDSS and have an RDS(on) of about 0.18 Ω (the latter depends upon which manufacturer's datasheet you look at).

The tank transformer, T1, consists of two windings, 5 turns each, with the secondary winding wound inside the primary winding (the windings are concentric). Total coil length is about 2.75", and the inner-diameter of the outer coil is about 1.5". After I wound T1 I discovered that its inductance measured to be around 570 nH. I'd been shooting for about 400 nH, but the difference isn't a big deal -- 570 nH just lowers the overall Q a bit (from a simulated Q (with 400 nH) of 5 to an actual Q of 3.6 at 3.87 MHz with a 50 ohm load). (See note later in this posting regarding measuring inductance of an unknown inductor).

C7, which, in combination with C10, forms the resonant tank capacitance, is actually six 510 pf ceramic capacitors (low ESR caps from American Technical Ceramics (their 700B series)). C10 is an air variable (20-420 pf) from my junk box, and it gives me a tuning range of approximately 3.78 MHz to 4.03 MHz.

Peak voltage across these tank components is on the order of 80 volts or so, so there's no reason for high-voltage parts. However, current through the inductor and capacitors is on the order of 3 to 5 amps RMS (per my SPICE simulations), so low-ESR components are highly recommended.

The MOSFET Drains are fed via 18 uH inductors L1 and L2. I had wanted to use higher inductance, but I didn't have anything in the junk box that was suitable (high inductance and high self-resonant frequency (S.R.F.)). However, I did have a couple of J.W. Miller 5252 inductors -- these are 125 uH inductors, but their self-resonant frequency is only about 2.5 MHz. I removed the top two winding layers (of three total layers) to give me an inductance of 18 uH and an S.R.F. of about 48 MHz.

I decided that the simplest way to drive the PA MOSFETs would be with MOSFET drivers. I chose IXDD414 MOSFET drivers (note: these are obsolete parts, but I found mine on Ebay). They drive the MOSFETs via 1-ohm resistors, which seemed to reduce ringing (but this observation really should be reconfirmed -- take it with a grain of salt).

To drive the IXDD414 Drivers I use two XOR gates to generate, from the VFO signal, two signals of the same frequency but 180 degrees out of phase with each other. One of the XOR gates inverts the VFO signal, while the other passes it through uninverted. Both XOR gates are on the same die, which should minimize the differential delay between the two signals.

The VFO signal is AC-coupled to an input on each of these two XOR gates, and two potentiometers provide variable DC offsets to each of these same two inputs so that the duty-cycle (i.e. symmetry) of each XOR output can be independently adjusted.

(Note: For testing I drove the XOR gates with an HP 8640B signal generator, set to +10 dBm. At this level, this generator provides a nice, very low distortion sine-wave with about a 4 Vpp amplitude (rather than 2 Vpp, which you'd expect at +10 dBm, because the 8640B is now terminated in a high impedance, rather than 50 ohms)).

The final bit of circuit on this page of the schematic, Q1 (a P-channel MOSFET), ramps the DC voltage feeding the IRF520 Drains up and down when the amplifier is turned on and off, thus providing a soft, rather than hard, transition to the output RF envelope. (I tried using the enable pins on the IXDD414 ICs in lieu of adding this MOSFET, but I found there were voltage spikes on the Drains of the IRF530 MOSFETs exceeding their VDSS when I transitioned these Drivers ON using their enable pins).

Page 2:

This page contains the voltage regulators and control circuitry.

An LM2576 switching regulator provides the +12VDC power for the IXD414 MOSFET Drivers. These two drivers require about 0.4 - 0.5 amps of current, total. A 12V linear regulator would have had to dissipate about 5 to 6 watts of power, which is why I chose to go with a more efficient switching regulator.

The values for the switching-regulator's components are straight out of the LM2576 datasheet. Note that this datasheet specifies a 1000uH inductor for the 12V regulator when the input voltage is around 26V and the load current around 0.4 Amps. Pulse Electronics has a series of "50 KHz Inductors" (available through Digikey) that are recommended for LM2576 applications. I used the PE-53120, which is a 1000 uH inductor.

A 7805 5-volt linear regulator provides 5VDC for the digital logic.

This amplifier is designed to be keyed by my 813 AM transmitter. Because I want the VFO to be inaudible in my receiver when I'm not transmitting, I need some way to disable it (or move it off frequency) when I'm not transmitting. Also, I want the VFO to be enabled and generating its signal before I apply power to the MOSFET Drains and to go OFF after I remove power from the MOSFET Drains when I'm done transmitting, so that the VFO is stable at all times while power is being applied to the MOSFETs. In other words, I want to "nest" the MOSFETs' ON/OFF cycle within the VFO's enable/disable cycle.

Although I could use the 813 Transmitter's sequencer to nest the MOSFET Power ON/OFF within the VFO Enable/Disable, for ease-of-testing I decided to incorporate a sequencer into this design to allow me to test this amplifier as a stand-alone unit. This new sequencer is also based upon the W2DRZ design. In the future, when I incorporate this circuit into the 813 AM Transmitter, I will decide if I should use the 813 AM Transmitter's sequencer in lieu of this one.

This sequencer runs at a 50 Hz clock rate because I want it to run faster than the sequencer in my 813 Transmitter (which I've set to run at roughly a 10 Hz clock rate).

I plan to drive this amplifier with an N3ZI DDS Module, which I would like to disable when I'm not transmitting so that it doesn't interfere with reception. There are a couple of ways that this might be done. One is to shift the VFO to a completely different frequency (using the DDS Module's "VFO B/A" input).

Moving the VFO off frequency when not transmitting would prevent Receive interference, but it might be also useful to shut off the VFO when transmitting so that the MOSFET Drivers (which are driven by the VFO via the XOR gates) aren't consuming power from the 12V supply. There are several ways in which one might do this:

One way might be to "lift" (via an open-collector/drain driver) the ground-end of R1, the 6.8K resistor attached to the AD9834's FS ADJUST pin (pin 1), when not transmitting. Per the AD9834 datasheet:

(FSADJUST = 1.15V nominal, and
RSET is R1 in the N3ZI DDS2 VFO schematic)

Thus, raising the resistance of R1 during Receive should reduce IOUT to near zero.

Another possible way to disable the VFO might be to simply short the IOUT output from the AD9834's IOUT to ground. This is a current-source output, of which the DDS chip has two (IOUTB is the second one), and the datasheet states that IOUTB can be shorted to ground if not in use, so I would think that one could also short-out the first output, too, to disable the DDS (both are rated at the same output current). But is this advisable? I can't say. Also, the current at IOUT would still be generated and thus sourced out the IOUT pin, and so any "non-zero area" current-loop formed by the "shorting" components and IOUT's signal path could still create some amount of interfering RF emissions on the receive frequency.

And perhaps the easiest way would be to simply take the IXDD414s' EN pins (pin 5) to ground at the same time that the VFO frequency is shifted (i.e. VFO disabled).

There are some signals on this schematic page, such as MUTE VFO, that could be used for just this purpose (e.g. tie MUTE VFO to the U8.5 / U9.5 node). I'll determine which route is best when I incorporate the N3ZI DDS module.

Notes on Construction:

I built the circuit on a piece of 6.5" x 4.5" scrap single-sided copper-clad FR4 circuit board. The copper plane on this board is used as the circuit ground. I cut up pieces of double-sided FR4 PCB material to use as mounting pads and power busses (one side of each is soldered to the copper "ground plane" on the main board).

Regarding the MOSFETs and their MOSFET drivers (and any other components with high slew-rate signals), it's important to minimize parasitic inductance, so keep leads as short as possible.

Caps used for power-supply bypassing (e.g. C23-C26, C29 and C30) should have very high self-resonant frequencies, and they should be mounted as close to the IXDD414s power pins (and ground) as possible to minimize unwanted inductance from their leads.

It's a good idea to try to ensure that each Drain of the IRF530 MOSFETs sees approximately the same amount of capacitance-to-ground from the wiring and other sources -- my SPICE simulations showed that unequal amounts of capacitance-to-ground for the two MOSFETs results in unequal voltage peaks, with respect to ground, at the Drains of the MOSFETs.

The IRF530 MOSFETs are attached to a heatsink consisting of a copper buss-bar that's 1" x 4.75" x 0.125". This heatsink is electrically attached to the circuit ground with copper tape and also a small angle bracket that mechanically holds the heatsink to the circuit board.

The transformer T1 is constructed of rectangular 3/16" x 1/16" enameled copper magnet wire (this is the same wire used by Taniguchi, Potter, Rutledge in their 200 W Power Amplifier which appeared in the Jan/Feb 2004 issue of QEX). It consists of two windings, 5 turns each. Total length is about 2.75", and the inner-diameter of the outer coil is about 1.5". The secondary-winding is closely wound inside the primary winding (to minimize leakage-inductance), and I covered one of the windings with Kapton tape when I found that the wire's enamel was sometimes cracking as I bent it, and I was concerned that the two windings might short-out to each other.

The LM2576 datasheet has useful tips for layout and interconnection of components.

Adjustments and Tuning...

There are three adjustments to make: The two Symmetry potentiometers, R3 and R6, set the duty-cycle of the outputs of the two XOR gates, and the Tune variable capacitor, C10, in the output Tank Circuit allows the Tank's resonant frequency to be tuned roughly 250 KHz.

Initial Setup:
  • While not transmitting (PTT IN is still high), I first set the two pots, R3 and R6, to midway in their adjustment range. While monitoring the XOR outputs with a scope, I then I tweak the two potentiometers so that the outputs of the XOR gates are each at (or close to) a 50% duty-cycle.
  • I then take PTT IN low to enable the transmitter. While monitoring the two Drain waveforms on an oscilloscope, I tweak the two pots to try to minimize the "ringing" on the MOSFET Drain signals. (See note below regarding how to accurately probe the Drains). Note: The final setting of each pot seems to correspond to a duty-cycle very close to 50% for each XOR output.
  • Then I adjust the frequency of the VFO for minimum Drain current (using a voltmeter across the 0.1 Ω resistor, R12, to monitor DC Drain current).
  • I again tweak the pot adjustments to again minimize ringing on the two Drain waveforms. (If you have a Spectrum Analyzer, you can also monitor the spectrum (out to, say, 100 MHz) and adjust the pots to minimize the higher-frequency spikes).

The result should look something like this:

(Click on image to enlarge)

Once these adjustments have been made, I find that I can keep the pot settings fixed and only change C10 when I move to a different frequency. (When moving to a different frequency, you can try retuning C10 for minimum Drain current, but I personally find that approach only gets me into the ballpark. The approach I follow is described in more detail just a bit later in this section.

Per my measurements, the efficiency of the MOSFET amplifier itself is around 90% (this number should be taken with a grain of salt, as it depends a great deal upon the accuracy of your watt-meter as well as DC current and voltage measurements!), and efficiency drops to about 86% at about 100 KHz of either side of the frequency to which C10 is tuned to. However, ringing is starting to look pretty severe at this point, and so I'd recommend changing the VFO by no more than, say, +/- 50 KHz before retuning C10.

When misadjusted, the Drain waveforms can look like the following image (or much worse!). Note that this is ringing on the waveform, not oscillation.

(Click on image to enlarge)

When changing frequency, I only adjust the capacitor, C10. The two pots I leave alone after their initial adjustment (see above).

When tuning to a new frequency, my procedure to adjust C10 is a bit iterative. You can try to adjust it for minimum Drain current, but I find that this approach doesn't always work. Instead, I do the following:
  • Rotate C10 to where you think it should be, approximately, for the frequency you'll be using.
  • Tune the VFO for minimum Drain current.
  • If the frequency of the VFO, after tuning, isn't close enough to where you'd like to be, tweak C10 a bit and repeat.
This approach seems to work for me.

Knocking Down the High-Frequency Junk

The output of the Class E/F amplifier is fairly dirty with high-frequency trash from 1) Harmonics (and ringing) on the MOSFET Drain waveforms, and 2) pickup of harmonics from the XOR gates and MOSFET Drivers.

Here's the spectrum of the Amplifier's output prior to adding an external filter.:

(Click on image to enlarge)

(Measurements made through a 30 dB Bird attenuator. The signal at the far left is the fundamental (at about 3.8 MHz), and the next signal (very low level) is the second harmonic.)

The above chart shows spurs out to 100 MHz. In reality they extend well past this frequency. In an attempt to reduce them, I first tried a 5-element Chebychev low-pass filter from the tables in the ARRL Handbook (Fig. 12-19, #7, for fco of 4.5 MHz, which results in values of 620 pf for the input and output caps, 1200 pf for the middle cap, and 2.39 uH for the two inductors).

But when I tried using this filter, I had to crank up my power-supply to about 30 volts to get the same amount of RF power output. So I nixed this filter (The peak Drain-Source voltage for the IRF530 MOSFETs was at its limit).

Instead, I decided to incorporate a simple diplexer, similar (in topology) to the one described in the Part 2 article of the High-Efficiency Class-E Power Amplifiers. . To keep the design simple, I designed for a Q of 1, which means that the inductors and the capacitors are the same in both "halves" of the diplexer. Here's its schematic:

(Click on image to enlarge)
The caps are dipped silver-mica (300V rating), and the inductors were wound with 26 gauge enameled wire. I'm using a BNC-mounted Tek 50 ohm, 1/2 watt termination to terminate the parallel L-C branch of the diplexer. After about 1/2 hour of "key-down" operation, this termination gets a little bit warm.

With this filter, the PA requires a DC Power Source of about 25.7 VDC to generate 39 watts RF Power out.

And here's the resulting spectrum:

(Click on image to enlarge)

Because of its low Q, the Diplexer doesn't do much to knock down harmonics that are near the fundamental, such as the 2nd and 3rd harmonics. But because of the symmetrical output of a push/pull amplifier topology, the 2nd harmonic is already quite far down (when the Symmetry pots are properly adjusted), and the 3rd harmonic is now more than 40 dB below the fundamental.

One advantage to a diplexer implementation is that it presents a near 50 ohm load to all frequencies (assuming that the external load presented to the series L-C filter is 50 ohms at its resonant frequency). This can help stabilize an amplifier that might otherwise be unstable when presented with off-frequency unknown impedances.

Accurately Probing the MOSFET Drain Voltage Waveforms

If you try measuring Drain voltage waveforms with a standard scope probe and its ground lead, you are not going to get an accurate picture of what the waveform actually looks like. Instead, you are very likely to see all kinds of junk on the signal. This "junk" really isn't on the signal -- it's radiated noise picked up by the inductive "loop" formed by the scope probe and its ground lead.

To get an accurate picture of how the signal really looks, you need to minimize the capture area of this loop. The best way to do this is to keep the ground "lead" as short as possible, and connect ground to the probe as close to the probe tip (where the signal being probed is) as possible.

For this purpose I adapted a Tektronix PCB to probe-tip adapter (Tek p/n 131-4244-00, made for probes such as the P6139A). I soldered two pins of the four-pin "ground" shell to the PCB copper-clad upon which I'd built the amplifier (the other two pins are in the air, as you can see in the photo below), and the socket for the probe tip I soldered to the Drain buss for one of the MOSFETs. The other MOSFET has the same setup so that I can monitor both Drains simultaneously.

(Click on image to enlarge)

(There's a useful app note from Analog Devices here. Although it discusses probing high-speed signals, its techniques are quite applicable to this circuit, too.)

Other Notes and Thoughts:

1. Measuring Inductance or Self-Resonant Frequency of an inductor:

Here's the technique I use. There might be better approaches, but this one worked for me...

(Click on image to enlarge)
2. Tank Capacitors:

Per my SPICE simulations, the tank circuit has large currents -- on the order of 3 to 5 Amps RMS. So you want the tank capacitance to have a very low ESR to minimize unwanted power dissipation.

For my tank capacitance, I used six 510 pf caps in parallel. The capacitors are manufactured by American Technical Ceramics, and are from their 700B series. The ESR of their 510 pf capacitor is in the range of 0.04 - 0.05 Ω. If we assume 0.5A of current passes through each cap (ball-parking 3A RMS total current through six caps), the power dissipation in each is then on the order of 0.01 watts. Not too bad!

(In hindsight, though, I probably should have used their 470 pf caps. The 510 pf caps have a working voltage of 100 volts, which is a bit too close to the voltage they're actually seeing in this circuit (see scope images above of the Drain waveforms). The 470 pf caps, on the other hand, have a working voltage of 200 V, which gives a nice margin. If I can get these caps in, I'll replace the 510 pf caps.)

3. IRF530 MOSFETs: These have a max VDSS of 100V. I'd like to have a bit more margin (per the discussion above regarding the 510 pF capacitors), but that's what was in the junk box when I looked for suitable parts. We'll see if there's any issue with reliability.

4. Some useful formulas:
  • For a resonant circuit: L = 1 / [ (2*π*f)2 * C ], or C = 1 / [ (2*π*f)2 * L ]
  • For a series RLC circuit, Q = (1/R) * √L/C, which, when combined with either of the two equations above, gives us: Q = |X/R|.
  • For a parallel RLC circuit, Q = (R) * √C/L, which, when combined with either of the two equations above, gives us: Q = |R/X|.
  • Note that when Q = 1, R = |X| for both the series and parallel RLC circuits.
5. 24V vs. 12V Power Supplies:

This design could be run from 12V (e.g. 13.4 VDC) rather than 24V (actually 26V) by changing the design of T1 to transform the 50 ohm load to a lower resistance across MOSFET Drains. This approach has two advantages: 1) Lowers the peak-voltage across the Tank components and at the Drains of the MOSFETs, and 2) Eliminates the need for the 12V switching regulator.

However, with the 24V supply, I can adjust the supply's output voltage (typically +/- 10%) to vary RF Output Power independently of the 12V supply (in case there are other radios running on the same 12V supply that might depend upon that voltage being fixed). Also, use of a 24V supply means that the transformer T1 for this application has a turns-ratio of 1:1, which (in my mind) simplifies its design. It would need to be on the order of 1:4 for a 12V application.

6. Transformer T1:

T1 consists of two concentric solenoid coils, air-wound with thick wire to minimize losses. It's possible that this transformer could be wound on toroidal or balun forms instead, using smaller gauge wire than the very large rectangular magnet wire that I used. It would be interesting to see what the effect of such a transformer would be on overall efficiency. Perhaps someday...

7. RF Power and Efficiency versus Power Supply DCV:

(Click on image to enlarge)
  • DC Voltage measured at the Q1 side of L1 and L2.
  • The burbles in the efficiency curve are probably due to measurement errors on my part.




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Class E Amplifiers:

Class E/F Amplifiers:


1. I could have easily have made a mistake, so please regard (and use) this design accordingly.

1 comment:

Anonymous said...

It is a useful article. thanks. Agus HY