Wednesday, August 16, 2017

An FPGA SDR HF Transceiver, Part 8 -- Front Panel, Rear Panel, and Other Schematics

In this eighth blog post in my FPGA SDR Transceiver series, I will describe the Front Panel and its Arduino processor (and associated circuitry), the Rear Panel, and other circuitry within the radio that interconnects front panel with rear panel.

(Part 7 of this series is here: Part 7)

Before I begin, let me again acknowledge Dick Benson, W1QG.  Dick is the father of this design, and although I've made some modifications to the FPGA logic, the underlying architecture and the vast majority of the Simulink implementation is Dick's.

A note regarding the schematics...

These schematics were drawn using the Lite version of Cadence's Orcad Capture.  This is the free version of the program, and it limits a schematic's number of nets to 75 and the number of parts to 60 (limitations which apply if you want to save the design, which I always do).

Because this radio design has many more nets and parts than the 75/60 limit specified by Cadence, I have broken the overall design into smaller "bite size" schematics, each  independent of the others and each drawn on a single A-size sheet.

But because I've broken up the design into smaller independent pieces, I can not use Capture's Design Rule Checker to check the overall design for design flaws.  Therefore, there is the possibility that errors have crept into the schematics.  So be aware!


The Front Panel provides the User Interface for the radio, and it is designed to be a separate sub-assembly that can easily be removed from the chassis.

An Arduino Nano processor provides the user-interface processing, and it is tasked with reading the front and rear panel controls, displaying information on the LCD, and communicating with the FPGA.

Let's take a look at the schematics...

Front Panel Main (Nano) Board Schematics:

(Click on image to enlarge)

Notes on the "Main" board schematic:
  1. +12V is supplied to the board via J11 in the lower right-hand corner.  This +12V will also power the FPGA board (via header J1).
  2. +5V is also supplied to the board from a separate source (via J12) -- the Arduino Nano's on-board 5V regulator cannot supply the current required at 5V for the front panel, and so a separate switching power supply provides this assembly's 5V power.
  3. J1 is the primary interface to the FPGA board, and it supports the 4-wire Control Interface, provides +12V to the FPGA board, and carries other miscellaneous IO signals (such as mic audio) between the FPGA board and the Front Panel.
  4. Note that the FPGA Control Interface is a 3.3V interface, whereas the Arduino's IOs are 5V.  R9 and R10 (in conjunction with terminating resistors on the FPGA board) divide down the 5V control signals sent from the Arduino to be 3.3V compliant for the FPGA, and U2 and U3 provide a level translation of FPGA 3.3V output signals to input levels compatible with the Arduino's 5V IO. (Note that the Arduino's ViH spec is 3.0V, minimum, which is slightly higher than the Xilinx FPGA minimum VoH spec of 2.9V.  Thus the level translators to ensure that the Xilinx outputs meet the Arduino's ViH spec.) 
  5. U4 provides 3.3 volts for the Main board.
  6. The front panel's Volume control provides a voltage that is converted to digital by the Arduino (and then sent to the FPGA via the 4-wire Command Interface).
  7. Transmit SWR and Forward Power can also be sampled by the Arduino's ADC via connector J6.  (At this time this feature is not used for monitoring power and SWR.  Instead, these pins are used to measure the input DC Voltage (e.g. 13.5 VDC).  This feature is described further, below, in the Interconnects 1 notes).
  8. The board also has a buzzer, LS1, to provide various beeps when I press buttons or when error conditions occur.  The Arduino pin driving this beeper can also be used to "calibrate" the Arduino's ADC readings  (to compensate for the actual ADC reference voltage -- necessary if trying to use VRL and VF to calculate SWR and Forward Power).  Its function is selected via header J10.
  9. There are simple one-pole RC filters on many of the IO signals to mitigate susceptibility to RF fields that might be coupled onto external cabling and leads.
  10. LED D2 is an on-board LED used only for debugging and is not visible during normal radio operation (its function is duplicated by a second LED, to be described later, below).

(Click on image to enlarge)

Notes on the "IO1" Schematic:
  1. This schematic shows two headers that provide IO signals to the Arduino.
  2. The upper header, J21, connects to the rotary encoder used for frequency tuning (this is an Oak/Grigby Rotary Optical Encoder, Model 91Q128-43-00110, that provides 128 pulses per revolution).
  3. The lower header, J22, connects to the two front-panel mechanical rotary encoders and the analog meter.  These rotary encoders include push-button switches and are used to select menu items via the LCD.  (They are similar to those used in the Keyes KY-040 rotary encoder module).
  4. Again, simple one-pole RC filters attenuate any RF that might be coupled into the circuitry via external wiring.

(Click on image to enlarge)

Notes on the "IO2" Schematic:
  1. There are more IO signals than there are Arduino IO pins: U1 is an IO expander (PCF8575) that allows the Nano access to the additional IO signals.  It communicates with the Arduino Nano via the Nano's I2C interface.
  2. The RST signal from U1 is a high-true Reset signal, sent to the FPGA board, used for resetting the FPGA's Communications Interface.  Note that the PCF8575 cannot drive its output pins high, so a pullup is needed (R23).
  3. The Arduino also communicates with the LCD via I2C (using an external I2C to parallel converter mounted at the LCD).  Header J2 provides this interface.
  4. Header J16 provides an extra I2C connector.  It is not used at this time.
  5. The microphone audio attaches to the Arduino board via header J13.  Note that the microphone audio is not used by the Arduino -- instead, this signal is simply routed to the 26-pin FPGA interface connector, where it is sent to the FPGA board (and converted into a digital signal).  By the way, this MIC_AUD signal is not from the mic connector itself, but from a separate mic preamp board that will be described later, below).
  6. U4 provides "clean" 5V that can be used to power an active (FET) mic element.  This feature is not used at this time.
  7. Transmitter keying is controlled via the Arduino, and the signal nPTT (low true) is used both in CW and Voice modes to signal the FPGA (via the Arduino) to Transmit.  Because this signal can come from the outside world, I've added ESD protection with TVS1.  (R8 provides both RF filtering and current-limiting if TVS1 were to clamp).
  8. And again, numerous simple RC filters on control lines to filter out RF that might be coupled onto cabling.
  9. The LED is only used for debugging and is not visible during normal operation of the radio.

Connector Locations:

For my own records, below are the location of the Main Board's connectors (shown in the three schematics, above):

Front Panel 5V Switcher:

The Front Panel's 5V requirements are supplied by a 5V switcher that converts 12V to 5 VDC.  (I had originally used an LM7805 linear regulator, but, given the 5V rail's load current, the 7805 was getting too hot for comfort even with a large heat-sink, and so I went the switcher route.

This circuit is mounted on a separate board within the Front Panel assembly (it is not on the Arduino "Main" board).

(Click on image to enlarge)

The circuit should be self explanatory.  For additional information refer to the LM2576 datasheet.

Front Panel Controls:

Now let's look at the wiring of most of the front panel's controls.  (The remaining controls will be described in the next section, below).

This circuitry should be self-explanatory...

(Click on image to enlarge)

(Click on image to enlarge) 

Front Panel Controls, Rear Panel, and Interconnects:

Below are the remaining front panel controls and connectors, as well as rear panel connectors and how they all interconnect.

(Click on image to enlarge)

Notes on the "Interconnections 1" schematic:
  1. On the rear panel, diode D1 provides protection against accidental reversing of the power supply voltage.
  2. J15, the "EXT. ON" connector, provides a signal for external devices that is low-true when the FPGA SDR radio is ON. 
  3. J3 provides a PTT port parallel with the front-panel's "Key" and "MIC" (PTT pin) ports.  Note that this signal, nPTT, is low true (low = xmit).
  4. The input DC voltage can be monitored (and thus displayed on the LCD) by the Arduino.  This DC voltage is sampled after the Schottky diode on the rear panel and then divided-by-four.  The resulting voltage, on Header J37, is connected to J6 on the Arduino board via a 3-wire cable.  Either J6 pin 1 or J6 pin 3 can be read by the Arduino's ADC, the ADC reading then multiplied by 4 (and with an offset representing the Schottky Diode D1's Vf drop added to this result) to represent the voltage at J34.

This next schematic, "Interconnects 2", details the audio output interconnections:

(Click on image to enlarge)

Notes on the "Interconnects 2" schematic:
  1. Speaker Audio from the FPGA board comes into this schematic via connector J12 (at bottom of schematic).
  2. LS1 is the radio's internal speaker (mounted on the top cover).
  3. An external speaker can be connected to the radio via J1 on the back panel.  Plugging in an external speaker will turn OFF the radio's internal speaker.  (Important note: the external speaker should be connected only to Tip and Ring of the stereo plug, NOT to ground).
  4. Although a stereo connector (J2) is used for the headphones, they are connected in MONO mode (left and right in parallel).
  5. And because the speaker audio from the FPGA board is differential with DC bias, this differential signal is converted to single-ended for the headphones by using just one side of the differential signal (against ground).  The DC bias is removed by C1 (i.e. the audio is AC-coupled to the headphone jack).
  6. R3 keeps the negative side of C1 at ground potential so that there isn't a loud "pop" in the headphones when they are plugged into J2.
  7. The SPKR ON switch turns ON or OFF any speaker (internal or extenal), but not headphone audio.  One side of this switch is read by the Arduino, and the switch status is sent to the FPGA where it is used to change the audio level when headphones are used.

Below is an image showing the interconnects in the two schematics above.

(Click on image to enlarge)

(Note some singeing on the wires going to J12.  Oops!  Also, J37 was originally a 4 pin header.  It has been trimmed down to 3 pins.)

The next schematic details the small "plate" (actually double-sided PCB stock) upon which two RJ45 connectors are mounted:

(Click on image to enlarge)

Notes on the "RJ-45 Plate" schematic:
  1. The two headers on the left-hand side connect to the main FPGA board (described in post 6 of this blog series).  The "Interconnects 3" and the "Interconnects 4" schematics can be found there.
  2. I plan to use an SDR1000 PA (plus a driver board) to amplify the FPGA SDR Radio's TX output up to 100 watts, peak power.  This PA and driver will be mounted in an external chassis and controlled by the FPGA SDR via connector J1 in the schematic (above), which will connect to the separate PA assembly via a shielded RJ-45 cable.
  3. I also have plans to build an external 500 watt solid-state PA.  Similarly, it will connect to J5 in the schematic (above) via a shielded RJ-45 cable.
  4. To prevent EMI coupled onto external wiring from getting into the radio, all IO from the RJ45 pass through simple one-pole RC filters.  These should be placed as close to the RJ45 connectors as possible.

*** Schematics of additional rear-panel connectors will go here.

I'm using a scrap HP 37203A HP-IB Extender as the chassis for this radio.  The original back panel looked like this:

Currently, it now looks like this:

(Note that I am adding connectors as I need them, so not all connector locations are populated yet).

LCD Adapter:

To minimize Arduino IO pin usage, the Arduino communicates with the Front Panel LCD via its 2-wire I2C interface.

But because the LCD itself does not support I2C, I use an I2C Interface LCD Adapter similar to the one shown below and available via eBay:

This adapter is designed for use with LCD modules having a 16-pin SIP interface connector.  Unfortunately, the LCD module I chose has a 16-pin DIP interface connector.  So I wired an adapter board (that sits on the back of the LCD module) to convert the I2C Adapter's 16-pin SIP wiring to 16-pin DIP wiring:

(Click on image to enlarge)

Microphone Preamp:

Microphones typically generate low-level audio.  Although the FPGA could internally amplify a low level signal coming into it via the 16-bit audio ADC (the AK4554 Codec), this amplification (following the ADC) also increases the noise-floor underlying the microphone audio.

So I've added an external Mic Preamp (prior to the audio codec) with three levels of gain:  26 dB, 16 dB, and 6 dB.  Its circuit is below:

(Click on image to enlarge)

Notes on the Microphone Preamp:
  1. An on-board 5V regulator (U2) provides "clean" power for the preamp circuitry. 
  2. The op-amp (U1) has rail-to-rail outputs.
  3. One half of the op-amp (U1A) is not used.  I prefer not to have floating inputs on ICs, so I've connected it in a non-inverting configuration with its output set to 2.5V.
  4. The MIC IN connector (J2) connect to the front panel microphone jack.
  5. The MIC OUT connector (J1) connects to the Arduino board, which passes the amplified microphone audio to the FPGA board and the audio codec there.
  6. TVS1 provides ESD protection against an ESD event occurring on the external MIC signal.
  7. The circuit originally started out with gains of 0, 10, and 20 dB.  I increased these by 6 dB by paralleling the original R8 (20K ohms) with another 20K (because it's easier to piggyback surface mount components than to remove and replace them), and then changing the input series capacitance from 200 nF (two 100 nF caps in parallel) to 400 nF (four 100 nF caps in parallel), to keep the high-pass cutoff at 40 Hz.


The HP case I'm using for the radio is not large, and so to install the Front Panel and its circuitry some creative assembly was required.  The photos below show what is involved...

First, here is the Front Panel with controls, LCD, encoders, and LCD Adapter and 5V switcher mounted (the 5V switcher is mounted (on standoffs) above the Frequency rotary encoder and the LCD Adapter is mounted (on standoffs) above the LCD module):

Next, mounting (on more standoffs) the Main (Arduino) board and the Mic Preamp board above the LCD Module Adapter and 5V switcher boards:

And finally, connecting all of the cables!

(Oh what a tangled web we weave!)

OK.  That's it for this blog post!

Background Notes:

SDR Notes:  Weaver Modulation and Demodulation
SDR Notes:  The Mixer Mathematics of Digital Down Conversion

Posts in this Series:

Part 1: Overview
Part 2: FPGA Modulation and Demodulation
Part 3: Interpolation and Decimation Filters
Part 5: Control Interface, Etc.
Part 9: 50 dB HF RF Power Amplifier

Standard Caveat:

I or Dick might have made a mistake in our designs, equations, schematics, models, etc.  If anything looks confusing or wrong to you, please feel free to comment below or send me an email.

Also, I will note:

This design and any associated information is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.