Friday, September 11, 2015

Antenna Auto-tuner Design, Part 7: Build, Phase 1


The build finally starts!

I'm breaking the build of my auto-tuner into 3 phases.  This post will describe phase 1.

Phase 1 includes building the basic L-network and control circuitry, and it will let me test the L-network and its tuning under "manual" control.  It will include the following circuitry:
  1. L-Network (capacitors, inductors, and their relays).
  2. AC-to-DC power supply.
  3. Front panel "manual" tuning controls.
I also mounted the meters (and LEDs) for Match Detection and other controls for Automatic Operation on the front panel, but these won't be wired up until Phase 2 and Phase 3 of this build.

The Schematics:

First, a note regarding the schematics...

I drew the schematics using the free version of ORCAD (I've used the paid-licensed version professionally for many years).  The free version limits the number of parts used in a design, so for this project which uses a greater number of parts, I've split the schematic-capture into multiple designs, rather than a single design.

This means that reference designators are often re-used, which is OK -- just think of them as being page specific.

But it also means that I cannot use ORCAD's "Design Rules Checker" (except within a page) to check my design for errors.  So...schematic errors might exist!  If you come across something that looks wrong, please let me know.

And now, on to the schematics...  

Click on any image to enlarge.

Schematic, the L-Network:


General Notes on the L-Network:
  • The L-Network now has a new Series-Capacitance section that is in series with the Series-Inductors.  More on why I've added this later in this post.

Notes on the Parallel Capacitors:
  • Initially the caps were from Vishay's QUAD HIFREQ series (readily available from Digikey).  When purchased from Digikey, the maximum value available (at 1000 V breakdown) is 180 pF in a 1111 case size.  So to create the larger values that I required I simply paralleled the appropriate number of 180 pF caps.  (Note that this won't increase Q, because although ESR is reduced by the number of paralleled caps, so is capacitive reactance, and so they cancel out when the new Xc is divided by the new ESR.)
  • Before I purchased the Vishay caps I had placed an order with ATC for samples of their 800C series NPO Ceramic High RF Power Multilayer Capacitors (their 700C series should be fine, too).  This series has a much larger case size than the maximum Vishay case size of 1111 available from Digikey, and they have excellent voltage and ESR specs (see graph below) and thus should have excellent Q, too.  Unfortunately, there was a very long lead time for these samples, which is why I instead started my build with the Vishay Quad HiFreq series, intending to replace the Vishay caps with the ATC 800C-series samples when they arrived.

The ATC caps arrived!  Here's an ATC 800C-series capacitor side-by-side with a Vishay Quad Hifreq capacitor.  The ATC cap is the larger of the two.



Notes on the Series-Inductors:
  • The schematic shows the inductors not quite in sequential order.  I moved a couple around to improve board layout, and I've reflected these changes in the schematic above.  And note that the circuit is designed so that, even while relays are switching, the transmitter attached to the tuner's input will never see an open circuit (unless, of course, there is nothing attached to the tuner's "Antenna" port).
  • Inductor values have changed from those selected in my previous post -- for example, the largest inductor is now 4 uH instead of 3.2 uH, mainly to create values that I could wind using "integer" number of turns. 
  • I used Excel to calculate each inductor's maximum voltage, per band, assuming 200 watts into a 10:1 SWR (I calculated inductor-voltage around the SWR circle to ensure I found the maximum voltage -- more information on these calculations can be found in my earlier blog post here). Then, using the "Mini Ring Core Calculator" program (available online), I generated the following table (listing inductor details for various core options) for my new toroidal inductor values:
    Numbers in RED signify core temperature rises that exceed my design constraint of a 50 degrees C rise above the 'inside the case' ambient temperature (itself assumed to be, worst case, 50 degrees C).

    Due to space constraints I decided to go with T157 core sizes for the three inductors, even though the 1000 nH inductor, when wound on a T154-17 core, exceeds my target core-temperature limit.  But it doesn't exceed it by much, and my rational for using it in lieu of a larger T184 core is that it's unlikely that I'll actually exceed the 50 degree C core temperature rise limit because, on the frequencies where this temperature rise is an issue I'll be operating either SSB or CW, neither of which will be at the worst-case of 200 watts of continuous carrier assumed for these calculations.

    When I wound the toroidal coils I discovered that the turns-count required to achieve the target inductance wasn't exactly the number predicted by the "Mini Ring Core Calculator" program.  Here's a summary of the inductors, their actual turn counts, and their predicted power loss (wire loss is calculated from skin effect and assumes a current of 6.2A -- 200 watts into a 10:1 SWR load).
     
    You might notice that I haven't included inductor Q measurements.  Although I have a couple of ways to measure Q, I decided to use my HP 4191A to measure inductor Q along with inductance.  But I have not included these results because, as it turns out, there can be a large amount of uncertainty in the 4191's Q measurements.

    A quick explanation:  the 4191A is essentially a single-port vector network analyzer measuring Gamma, and this Gamma measurement is then converted into component parameters.  If there is error in the Gamma measurements there will be a corresponding error in its calculation of component parameters such a inductance, capacitance, D, and Q.

    Dick Benson, W1QG, wrote a Matlab program to calculate error in the 4191A's Q calculation against error in the 4191A's Gamma measurement.  Assuming as an example an inductor of 4.7 uH that is measured at 5 MHz, very small amounts of error in the magnitude of the reflection coefficient can result in large errors in Q.   Here's the plot from Dick's Matlab routine:


    My conclusion from the graph above -- given a "typical" Gamma Magnitude accuracy of 1.1E-3 (plus a frequency dependent fudge factor, per the specifications listed in the "HP Journal" for January, 1980), is that, although the HP 4191A is useful for quickly determining component values at RF frequencies, its Q accuracy is suspect for high-Q measurements.

    If I can ever bring myself to unsolder my inductors from their board, I'll run a set of Q measurements using a different Q-measurement technique and I'll publish the results here.
    • And a note on toroidal coil winding.  The 1 and 2 uH coils were wound the "standard" way.  That is, start at one point on the toroid core and work your way around the core, winding as you go.  
    But my 4 uH coil (used only on 80 meters) was wound differently -- I started the coil as one normally would, but half-way through the winding process (and halfway around the core) I brought the winding across the width of the core and then started winding in the opposite direction.  The physical result is that the coil's two leads are far apart, rather than close together (as they would be with normal winding).  [This is a technique I first saw mentioned, I believe, back in the 1970's in Ham Radio Magazine, but I have no idea which issue it might have been.  (Update:  Russ Sherry, NM6DX, believes the article might have been "Simple and Efficient Broadband Balun", by Joe Reisert, W1JR, in the September, 1978 issue of Ham Radio magazine).]  
    Below is an image of the technique, crudely rendered by me.  Note that the B-field continues with the same orientation after the cross-over.  If the coil were wound incorrectly, the fields in the two windings "halves" would buck, and that would not be good.

    Winding a toroid inductor in this fashion has several positive effects (although if winding a balun you might not want to do this.  See here:  http://www.w8ji.com/toroid_balun_winding.htm. But I'll note, too, that W8JI's winding technique, although similar to the W1JR technique, is also a bit different.)
    1. The coil's "one-turn" effect should be minimized (the inductance of a normally-wound toroid is actually the "sum of the inductance due to the field inside the toroid plus the inductance of a single-turn loop around the center hole of the toroid." (quote reference here).
    2. Distributed capacitance is minimized (you can read a bit about this here).  Reducing a coil's distributed capacitance should decrease the measured inductance of the coil.  In addition, it should lessen the frequency dependency of the coil's inductance (i.e. minimize the effect of the inductance value increasing with frequency), and it should also increase the coil's Self-Resonant Frequency.  
    In other words, if we include the effect of a coil's distributed capacitance, the impedance of the coil actually is:

    ZL = jωL * (1/(1-ω2LCd)). 

    That is, measured inductance can be thought of as the actual inductance 'L' increased by a factor of 1/(1-ω2LCd), where Cd is the distributed capacitance across the coil (assuming we're measuring below a coil's Self-Resonant Frequency).  Thus, if the equation's denominator is less than 1 (and it should be less than 1 if operating below the coil's SRF), the inductance is increased by a factor related to Cd (if Cd is 0, then the equation equals 1 and L should not change with frequency). 
    Should all three toroidal coils have been wound in this fashion?
    I don't believe so (but I haven't proved it).  I wound the 4 uH inductor this way because I wanted to decrease its inductance slightly to bring its value closer to being equal to two times the value of the of 2 uH inductor.  But I'm not sure that the other toroidal inductors should be wound in this style.  Note that solenoid coils also have a distributed capacitance, and so their inductance will seem to increase with frequency.  If I wanted the values of my inductors, solenoid and toroidal alike, to maintain (to some extent) their power-of-two relationship as frequency were changed, it seemed to me that, ideally, the toroids used on multiple bands should be subject to the same distributed-capacitance effect as were the solenoid coils.  On the other hand, the 4 uH coil is only used on one band, 80 meters, and so I was not concerned with its value changing (or not changing) with frequency.

    Notes on the Series-Capacitance:
    • The series-capacitance block was added when I discovered during testing that I needed to somehow cancel out parasitic series-inductance in the L-network (more on this in the Testing section, below).
    • When capacitance is added, I start with a base value of 180 pF and to that I add increments of 90 pF.  Therefore, when capacitance is being added, the relay for the first capacitor (180 pF) is always on.  And the circuit is designed so that, even while the relays are switching, the transmitter connected to the tuner's input will never see an open circuit (unless nothing is connected to the Tuner's "Antenna" port).
    • Capacitor values determined by the limited range of ATC 800C-series capacitors that I have on hand (values are: 11, 22, 43, 47, 91, 180, 360, and 680 pF).

    Schematic, the Relays:

    The relays have been split across two pages, mainly to accommodate the parts-per-design limitation of the free version of ORCAD.



    Notes on the relays:
    • Diodes have been placed across each coil to snub the coil's turn-off voltage spike and thus protect the 2N3904 drivers from over-voltage on their collectors (2N3904 V(BR)CEO is spec'd at 40 volts).
    • 0.1 uF caps are also across each coil, mainly to provide a low-impedance shunt to any RF that might get onto the control lines via magnetic-field coupling into whatever loop-area each pair of wires creates.

    Schematic, Inductor and Capacitor Selection Controls:



    Notes on the Inductor and Capacitor Selection Controls:
    • This selection allows either Manual or Automatic (via the to-be-added CPU) control of the L-Network Relays.  For Manual control, 5VDC must be applied to the "MANUAL" net.  The hex switches will route this 5V and turn on the appropriate NPN relay drivers.  For Automatic control, the "MANUAL" net should be left floating (there's a pulldown on a different schematic page) or connected to GND.  The CPU should then drive the NPN bases through its own "diode-or'ing" diodes (not shown, to be included in the CPU schematic).
    • The LEDs are connected to 12V rather than 5V to prevent possible reverse-voltage breakdown when a relay is not being driven.
    • Capacitors to ground at the NPN transistors' collectors and bases provide RF bypassing.
    • The 2N3904 transistors need to supply 40-50 mA collector current (30-40 mA per relay and about 10 mA for the associated LED).  Minimum Beta is assumed to be 50, which means they requires a minimum of 1 mA base drive.  In the above design, base drive is roughly 2 mA (which, by the way, should be adequate for driving the two NORM/BYPASS relays from a single 2N3904).

    Schematic, Other Controls:


    Notes on the other controls:
    • Selection of LsCp or CpLs configuration can be done Manually or Automatically, in a fashion identical to that describe for the Inductor and Capacitor Selection, above (e.g. float the "MANUAL" net (it gets pulled down by R10) and drive the transistors via diode-or'ing).
    • After I finished my build I realized that I should have provided for diode-or'ing of a CPU-generated control signal into the base of Q8, the relay-driver for the NORM/BYPASS relay.  Well, I forgot to do this, thus the note to add an additional open-collector driver on the to-be-designed CPU board to drive this net.
    •  Switch and LED explanations are noted on the schematic page.

    Schematic, Series-Capacitance Control:

    I discovered during my initial checkout of my design that there were times when I need to add different amounts of series-capacitance in addition to series inductance (more on this in just a bit), and that this would require an additional four relays and circuitry for their control.  Unfortunately, I had already fabricated my front panel and I had no room for additional controls.

    So I came up with a plan for the temporary re-purposing of one of the controls that was already on the front panel but not used in this "Manual Mode Only" incarnation (i.e. Phase 1) of the tuner -- the Auto/ARM toggle switch.

    So I've temporarily replaced the 3-position toggle-switch with a push button and digital logic that steps through the various combinations of  the four series-capacitance relays.  And I made use of 4 unused LEDs (more on THAT later, too) to display the status of those relays

    The control-steps are listed in the table below, as are the LED display "bits" and the amount of series capacitance they represent.


    Here's the digital logic that steps through the capacitor values per the table above:


    Notes on the Series-Capacitance Control:
    • The push-button is debounced with the two NAND gates (they form an RS flip-flop).
    • The relays are disabled (off) when not in MANUAL mode (i.e. in Bypass or Auto mode).
    • The counter counts from 0x7 (no capacitance -- caps shorted) to 0xF (811 pF series capacitance) and then cycles back to 0x7.

    The LED current of these four LEDs is set at 4-5 mA instead of the 10 mA used for the L and C LEDs (to differentiate them (by brightness, as well as location) from the other LEDs used to identify L and C values, as all these LEDs share the same 10-LED bar-graph arrays). 

      Schematic, the Power Supply:


      Notes on the Power Supply:
      • I wanted to power the tuner from the AC line, because it's so much more convenient for me to just plug a cord into an AC jack than to try to wire up to my DC supply.
      • But one worry with using AC:  Could I prevent AC line noise from being conducted into the box via the line cord and then coupled into the receiver's RF path?  So the AC connector is actually an integrated connector and PI-network filter (I also route the wires that carry AC from this connector/filter to 12.6 VDC transformer under copper tape that I've soldered to ground).
      • In case AC Line-noise is an issue, I plan to also provide for powering the tuner via an external 12VDC source. The connector is yet to be added, though. And note that only AC power is switched via front panel switch.  If 12VDC is supplied externally, it will not be switched on/off with the front panel power switch.
      • The 5V regulator supplies power for any digital logic and for the to-be-implemented processor.

      • Note, 10 Aug 16:  If I were to build another tuner of this design, I would probably use diodes with a bit higher current rating.  The average current through the rectifier diodes is right on the cusp of 1A when all "allowed" relays and LEDs are ON and with the tuner powered  by an external DC voltage of 15VDC connected via Jack J1. (Note that all relays are never on, due to either step-size or maximum Ls/Cp values allowed for a band).  The 1N4001 diodes are rated at 1A average forward current.  With the Tuner powered by an external DC supply of 15.0 VDC and the maximum "allowed" number of relays ON, the current through D5 is 0.97A.  This current drops to 0.90A if the external DC supply is reduced to 14.0 VDC.  So, although there is some margin, it's not much!  (Note, too, that if the internal AC supply is used in lieu of an external DC supply, the AC supply's output voltage will drop as its load increases, so that, with the maximum "allowed" number of relays ON, the DC current through the diode bridge is about 0.9A).


      And now on to the build itself...

      The Build, Case and Chassis Notes:

      The first step in the build -- deciding what sort of case it should have.  I have a number of "project" boxes that I've purchased inexpensively at various swap-meets over the years.  I decided to go with an old Hewlett-Packard case that is all metal, including its covers.  Its dimensions are:  8.375" (W) x 3.5" (H) x 10.5" (D).

      Here's the HP case, disassembled and stripped of (almost) all of its original circuitry:


      I'm keeping the fuse holder, although I moved it from the back panel's center to its side.


      Below I've replaced the original AC connector with a filtered one (to help prevent conducted-EMI from entering the enclosure via the AC line).  And I've filled the large holes in the original sides of the HP chassis with double-sided PCB stock using copper foil tape, soldered on each side of the PCB stock, to electrically connect the two sides of each together (this will later change to non-conductive material, as I'll describe further below):


      I'm adding a  front divider.  The front divider is also double-sided PCB stock with the two sides electrically bonded via copper foil tape soldered to each side, and will help isolate the RF circuitry from the control electronics (i.e. digital processor, when I get around to incorporating it).


      Double-sided PCB stock is also used to create a mounting plate (I haven't yet added the copper-foil tape to connect the two sides of this piece of double-sided PCB stock).  This decision will also later change!



      The Build, Front Panel Notes:

      Designing the front panel, starting with a cardboard mock-up.



      Take the cardboard mock-up and use it as a template for cutting holes in a piece of double-sided PCB stock...



      Create a nice front-panel overlay...


      (See this post for the technique I use:  http://k6jca.blogspot.com/2009/12/how-to-make-your-equipment-look-like.html ).

      Wiring up the front panel...


      Additional notes on the front panel:
      1. The meters are swap-meet finds.
      2. Two rotary switches (stacked vertically) select C and two rotary switches select L.  The rotary switches are each 16 position hexidecimal-encoded (Lorlin Electronics BCKS1020, Code 042,  purchased on eBay)).  The bottom switch of each vertical pair selects the lower "nybble" of a group of 8 relays, while the upper switch selects the upper "nybble" of those relays.
      3. LED bar graphs display the binary code of the 'ON' relays.  The bar graphs each consist of 10 LEDs, but only eight are used (because there are only eight relays for the inductors and ditto for the capacitors).  The left-most four LEDs display the upper nybble of relays, while the right-most four LEDs display the lower nybble of relays.
      4. To determine the total inductance and/or capacitance being used to tune for minimum SWR, take the minimum step size of each and multiply by the value shown in the corresponding display.  For example, the minimum inductance step size is (theoretically) 31.25 nH.  So, let's say the inductance display is 0x51 (81 decimal) -- the total series-inductance in the L-network would be 81 * 31.25 nH  = 2.53 uH.  And thus, at full-scale, the inductance would be 255 * 31.25 = 7.97 uH.  Capacitance is similar, and its calculation would use a minimum (theoretical) step size of 11.25 pF.  In this case full-scale would be 255 * 11.25 pF = 2.87 nF.
      5. The Power switch only switches 120 VAC.  I plan to add a connector to allow powering the unit via 12VDC, too, but this power-source will be "diode-or'd" into the existing 12 VDC power bus and will thus bypass the front-panel ON/OFF switch.

      The Build, Capacitor Board Notes:

      Because of the small size of the chassis, I've decided to place the capacitors and their associated relays on one board.  The inductors and their associated relays will be on a different board.

      I purchased some pre-drilled protoboards via eBay.  Here is the Capacitor board.  To improve creepage distance between high-voltage nets and low-voltage nets, I've removed some metal pads on both sides of the board (this can be done either with a drill or with the hot-tip of a soldering iron).


      Mounting the capacitor-selection SPST relays...


      30 gauge copper sheet (0.010" thick) hand-cut into strips for interconnects.


      Bottom-side of capacitor board.  This was my first iteration, in which I used Vishay Quad HiFreq capacitors (typically 4 or more in parallel to reduce ESR), as can be seen below:


      The ATC 800C-series capacitors then arrived.  I removed the Vishay caps and installed the ATC 800C-series caps instead:


      The unused board area I hope to use in Phase 2, when I incorporate Match Detection circuitry.


      The Build, Inductor Board Notes:

      The first build of my inductor board (it will change following initial test results):




      Interconnects use 12 gauge solid-core copper wire.

      Inductor board will mount here (and the copper-clad PCB stock I use for a mounting plate will late be replaced with one that is non-conductive, explained below in the Testing Section):


      The two wires poking through the mounting plate above will connect the Capacitor Board to the Inductor Board.

      Here's the original Inductor Board installed on the mounting-plate.


      A board sandwich!  But nothing seems to be shorting out.

       

      For reasons I will explain during the Testing section (below), I found I needed to redesign this inductor board to shorten the interconnects between relays.  I also discovered that I needed to add the series-capacitors in addition to the planned-for series-inductors.  Here are the new Series-Capacitance relays and capacitor piggy-back board.



      The relays are mounted vertically because there is no room on the Inductor Board for me to mount them horizontally.

      Below you can see this board mounted in the upper left-hand corner of my second-generation inductor board (the location of the two right-most toroid coils, by the way, will change yet again, moving in a bit from the side of the case in an effort to minimize parasitic shunt capacitance to ground).



      The Build, Other Notes:

      The AC supply converts 120VAC to 12 VDC.  A separate 5V regulator converts 12 VDC to 5 VDC.

      Starting to build up the AC power supply on the PCB that will separate the RF components from the control electronics...



      To connect the front panel control circuitry to the relays, I use twisted-pair wires which run from the control section to each relay to minimize loop-area -- my hope is that this will help minimize induced B-field currents created by high-power RF and thus keep them from wreaking havoc with the control electronics.

      The temporary circuitry to control the selection of the series-capacitance is mounted on the bulkhead plate (the same one to which I mounted the power supply).  In Phase 3 of this build (a future blogpost) I will replace this circuitry with a processor and associated electronics which will mount in the same location.


      I used short lengths of RG-142B coax  to connect the back panel SO-239 connectors to the network in and out ports on the Capacitor Board.   I used RG-142B because:
      1. It has an impedance of 50 ohms.
      2. It has a high voltage rating (1400 Vrms / 1900 Vpk) -- for my application I'm assuming a max voltage of 900 Vpk based on a max power of 800 watts, peak, into a 500 ohm load (i.e. 10:1 SWR).
      3. It has a diameter comparable to RG-58, so is more easy to use in tight spaces (compared to, say, RG-8).
      4. At 30 MHz, loss on a 3 inch length of RG-142B, given a worse-case current of 6.3 Amps into a 5 ohm load (i.e. 10:1 SWR, 200 watts applied power) should be about 0.8% of total power (assuming most of the loss is due to skin-effect on its 19 AWG center-conductor (calculator)).


      Testing:

      OK, everything's soldered and screwed together, time to start testing...

      First thing to test... the power supplies!

      5V Regulator:
      • Output is 4.97 volts.  Check.

      12 VDC Supply:
      • No LEDs ON, No Relays ON.  Measured voltage:  18.3 VDC.
      • All LEDs ON, All capacitor and inductor relays ON.  Measured voltage:  13.8 VDC, 0.96 Amps.  Ripple Voltage (on 12 VDC line) = 0.68 Vrms (1.92 Vpp).
      Note that at full ON, the 0.96 Amps at 12 volts is a bit close to the Radio Shack transformer's 1.2A rating.  But it's unlikely that this will be an issue, because I don't envision all capacitor and inductor relays to ever be ON simultaneously.  For example, if the tuner happens to use large values of L and C, the smallest values of L and C will  probably be "don't cares," and so these relays (and LEDs) can be OFF.

      Now to find out what impedances the tuner can match to 1:1.


      L-Network Testing:

      From Network Theory I know that if a network transforms an unknown impedance to 50 ohms, resistive, I can determine the value of that unknown impedance by terminating the network's "driven" port with 50 ohms (while keeping the network's values unchanged) and measuring the impedance at its "load" port.  The impedance I then measure should be the complex conjugate of the unknown impedance that had originally been connected to the network's "load" port.


      (Note that this is only true if the network is lossless.  If there is loss, then there will be an error term in the measured complex conjugate impedance.  But for this testing, I will assume that network loss does not significantly impact the complex-conjugate measurement).

      So, to determine which loads the Tuner will tune to a 1:1 SWR match, I just terminate the 'XMTR' side of the tuner with 50 ohms and step through the various values of the network components while measuring the impedance presented at the tuner's 'ANT' port with my 8753A Vector Network Analyzer (VNA).

      For each change of the network component values, this impedance measurement is transferred from the VNA to a Matlab routine running on my computer, which in turn converts the measured impedance to its complex conjugate.  In other words, the Matlab routine calculates the actual load impedance that would be transformed by those specific tuner settings to 50 ohms for the transmitter.

      To remove unknown effects of the interconnection from the SO-239 connectors on the back panel to the network's on-board ports, I drive and terminate the network as close to the network's ports as I can, as shown below.  And I've also installed the back panel and I have electrically connected it (and including all of the chassis metal attached to it) with copper straps to the RF ground on the boards.


      10 meters should reveal the worst-case performance, so let's look at that.  Here's a plot of the boundaries of the match space (incrementing the network's L or C selection-value up to 0x10):


      Yikes!  That is not a pretty sight!

      In other words, there's a significant region that is outside the network's 1:1 match-space...



      What was causing this poor performance?  As an experiment I shorted the inductor board's input to its output with a copper strap, as shown below.


      And the left-hand side of the two curves (i.e. L=0) are now closer! (Note that, although not annotated as such, the bottom curve is for the CpLs configuration).


      These curves were plotted with no inductance selected.  Clearly it was the parasitic inductance of the inductor board's wiring (that interconnects the relays) that was introducing the shift.

      Not much to do but bite the bullet an build a new inductor board, doing my best to minimize the wire length when in the "default state" (no inductors selected).

      Here's how this new board looked, before inductors were installed (by the way, the silver-mica cap attached to the upper port is part of my experimentation in series-C compensation).


      A quick test prior to mounting the inductors and (and prior to my adding series-C compensation).  The curves were still too far apart!


      Even with the new board designed to minimize inter-relay wire length, there's still too much parasitic inductance.   What choices were left?

      Well, given the case dimensions and the area available inside it for the L-network, I really couldn't picture a different layout.

      Or I could try replacing the 12 gauge interconnect wire with "rectangular" wire (cut out of, say, a sheet of 30 gauge copper (0.010 inch thick), which should have lower inductance (calculator here).  But back-of-the-envelope calculations didn't show much improvement (maybe 10 - 15%, roughly).

      So I decided instead to compensate for the parasitic series inductance by adding series-capacitance to cancel it out.

      (I later determined, given the value of the "optimum" series-capacitance for each band (see Smith charts below), that the parasitic series inductance is roughly 160 nH).

      The amount of series-capacitance would be selected on a band-by-band basis (no need to change it while within a band), and on the lower bands this series-capacitance would be shorted out.

      Fortunately, the ATC 800C series capacitor values that I had on hand seemed to be perfect for this compensation!  And four caps would be needed to cover 14 to 30 MHz:  2 x 180 pF, 91 pF, and 360 pF.

      So, with the series-C "piggy-back" board installed and also with the mounting plate made non-conductive (rather than double-sided copper-clad PCB stock), the outline of the 30 MHz match space became:

      SWR with no L and no C selected (i.e. there is only the 50 ohm termination plus parasitic effects) is 1.11:1.  Not bad!

      Note that for the above plot I'm still testing by driving and terminating at the capacitor board.  But during this test there was no electrical connection between the L-network and the tuner's metal chassis -- essentially, the chassis is floating from the network's RF ground.  I will soon discover that this setup gave me optimistic measurements.

      For when I added coaxial cables to the SO-239 connectors (now electrically connecting the L-network's RF ground to the chassis) and installed the case covers, the plot shifted and the "no L and no C" SWR has moved from 1.11:1 to 1.5:1.  A significant change!



      (By the way, I'd also tweaked the series-capacitance slightly, which is why the left-hand "no L" curves are closer in this plot than in previous plots).

      Clearly, connecting a mass of nearby metal (the chassis and covers) to RF ground was introducing a significant shunt capacitance from the tuner's circuitry to ground.  A larger case might have fixed this, but I decided I had made enough changes.

      So now let's look at the Tuner's Match-space on different bands with the tuner in its final configuration (case covers ON!).

      Here's my test setup for doing that.  The ANTENNA port ("A") is the driven port, and the XMTR port ("X") is terminated with 50 ohms.  (My homebrew "open" and "short" calibration standards are also shown and the top cover will be reinstalled before I make my measurements).


      I calibrated the HP 8753A so that its Reference Plane would be at the end of the coax cable.  But I really would prefer the Reference Plane to be closer to the network itself, otherwise there is a slight rotation around the center of the Smith Chart (a rotation that is worse at higher frequencies), due to the delay of the internal coax connecting the back-plate SO-239 to the network itself.

      Fortunately, the 8753A lets me compensate for this additional delay.  The interconnecting coax (SO-239 to Capacitor Board input) is about 3 inches of RG-142B (Velocity Factor = 69.4), so the delay is about 366 psec -- not much, but it introduces a noticeable rotation to the Smith Chart plot on 10 meters.


      With that explained, let's continue with plots!  I'm going to just plot the "no L" and "no C" parts of the match-space, because these are the curves that interest me the most.  Ideally they should be on the 50 ohms and 20 millimhos circles, as shown below :


      Also -- I usually just plot out a part of the possible match values, starting at L or C = 0 and going up to a value that will put me near loads that generate an 8:1 or 10:1 SWR.  The match-space plots can be extended towards the circumference of the circle (i.e. into higher and higher SWRs) by going to higher values of L or C, but for time reasons (after all, it is time consuming to make the plots) I chose not to.


      Below is the plot at 28 MHz.  Series-capacitance is 180 pF.


      Note that the "no L" (left-side) curves are essentially coincident.  That's good.  But the "no L and no C" SWR is about 1.5:1.  Again, this shift from an earlier 1.11:1 measurement is due to the shunt capacitance-to-ground added by the case covers and chassis.

      And you'll also note that, in the previous plot above at 30 MHz, the left-side curves diverge from each other a bit more than they do at 28 MHz.  This is because, as frequency is increased, the 180 pF capacitor looks more and more like a short and therefore has less and less of a compensating effect for the parasitic series inductance.

      Below, the plot at 24.9 MHz.  Series-capacitance is about 270 pF.  "No L and no C" SWR is about 1.4:1.


      Below, the plot at 21 MHz.  Series-capacitance is 360 pF.  "No L and no C" SWR is about 1.3:1.



      Below, the plot at 18.1 MHz.  Series-capacitance is about 540 pF.   "No L and no C" SWR is about 1.22:1.


      At 14 MHz.  Series-capacitance is about 810 pF.  "No L and no C" SWR is about 1.2:1.


      At 7 MHz.  There is no series capacitance, it's been shorted out -- I decided to make the "additional series-capacitance" threshold 14 MHz -- for that frequency and above I'd insert series-C capacitance, below that I would not -- a compromise made mainly for implementation reasons.  There is some separation of the left-side curves, but I decided it was acceptable.

      "No L and no C" SWR is about 1.05:1.


      10.1 MHz shows the worst-case separation of the left-side curves that can occur with no series-capacitance to compensate for the parasitic series-inductance.  Still an acceptable compromise, in my view, but barely.  "No L and no C" SWR is about 1.08:1.


      And finally, at 3.5 MHz.  "No L and no C" SWR is about 1.03:1.  Nice!



      Here's a more detailed look at the match-space at 30 MHz.  I've stepped through all the L and C values from 0x00 to 0x10.



      Some unevenness in gaps -- I could play around with squeezing or pulling coil turns to change inductance if I thought it worth the effort.  Also, I could extend the plot further out towards the boundary of the Smith Chart by increasing my stop-threshold from 0x10 to, say, 0x18 or 0x1F.

      For comparison purposes, here's a look at the match-space of my Elecraft KAT500 at the same frequency and with the same step-size (0x01) and end-point (0x10):


      The same number of steps cover a broader range, but there are a number of gaps in the coverage.

      (By the way, my KAT500 "no L and no C" SWR measures 1.57:1 in CpLs mode and 1.51:1 in LsCp mode).

      (For the KAT500 measurements the 8753A reference plane lies at the SO-239/BNC adapter (same location as shown in an earlier photo (above) with my tuner).  But there is no 'Port Extension' compensation added to the measurement.)

      Here's the KAT500 test setup.  Again, driving the tuner's Antenna port and terminating the Xmtr port in 50 ohms.


      Here's a screenshot of the Matlab program (it communicates with the HP 8753A network analyzer) and the Elecraft KAT500 Utility while testing was in progress.



      Testing, S21 Transmission-Loss into 50 ohm load.

      These tests were performed with an HP 8753A Vector Network Analyzer and an HP 85046A S-Parameter Test Set.

      After calibration, loss-into-50 ohms was measured in Bypass Mode and in Manual Mode (with the Tuner tuned for Minimum SWR in Manual Mode -- that is, by manually stepping through component values, searching for the minimum SWR).

      For comparison purposes, I performed the same measurements on my Elecraft KAT500 Tuner (Serial Number 1707).


      The SWR of my tuner, when in Bypass Mode, becomes worse with higher frequencies (although it's still less than 1.2:1, worst-case).  I'm sure it could have been improved by placing the two Bypass relays closer together and paying closer attention to layout.


      [Update, 21 October 2015:  Testing, Tuner Power Loss, 10:1 SWR]

      After several attempts to measure Tuner Power Loss, I settled upon the "Gp" measurement technique, as I describe in much greater detail this post: http://k6jca.blogspot.com/2015/10/notes-on-measuring-antenna-tuner-power.html

      Here are those result for both my tuner and, for comparison, my Elecraft KAT500:



      I can think of a couple of reasons why my Tuner Loss becomes a bit worse than the KAT500 at 15 and 10 meters, and I suspect it's either due to "skin effect" loss on my wiring or SWR-related coax-cable loss on the short length of coax running from my Capacitor board to the Tuner's "Antenna" SO-239.

      But this additional loss is in the range of about 0.1 dB (or less), and (for the moment) I don't believe it's worth the effort changing my design to reduce it.

      By the way, you can also find other Tuner Loss measurement techniques with corresponding results for this Tuner in the link just mentioned, above.


      Tests yet-to-be-done:
      1. Measure inductor Q.
      Inductor Q measurement is way down on my list of things to do, because it involves disassembling the tuner and unsoldering the inductors.  Not something I look forward to.


      Finished:

      Here are some shots of the build at the end of Phase 1:

      Top View of Tuner (Capacitor board):


      Bottom View of Tuner (Inductor Board):


      Note that the relays are grouped together to reduce the overall parasitic series-inductance when all inductors are shorted (relays off).

      And the two side plates and the mounting-plate are now non-conductive to reduce the capacitance between the tuner's wiring and ground.

      Auto-tuner with case installed:


      Auto-tuner displaying its LEDs:


      Note that the illuminated LEDs are:
      • Power ON (far right)
      • L selection: 0xF1 (Left-most 4 and right-most 4 LEDs of the left-side 10-LED array)
      • C selection: 0xC9 (Left-most 4 and right-most 4 LEDs of the right-side 10-LED array)
      • Series-C selection: 0x5 (0101 using the middle-two LEDs (they are dimmer, by the way) of each 10-LED array)
      • LsCp Configuration Selected.

      Lessons Learned:

      Parasitic series-inductance and parallel-capacitance can have a significant effect, especially (and unsurprisingly) at high frequencies!  For example, a very experienced RF designer, Russ Sherry, NM6DX, recently mentioned to me that solenoid coils really should be at least "two diameters" away from the case (or chassis) to prevent the surrounding metal from affecting coil Q.  My larger solenoid coils probably violate this rule of thumb (as does the Elecraft KAT500).

      Anyway, this being my first foray into a design like this, I did not appreciate what the parasitic effects might be.  Now I have a better understanding of them.

      Mitigating their effect in this design has been a challenge and not a completely successful one -- the issue of parasitic parallel capacitance, for example, has not been resolved.  I've deemed it acceptable at the moment, but I wonder...should I move the design to a larger case?

      Some larger cases

      And if I were ever to make a remote tuner, I'd seriously consider using a non-conductive case!

      Anyway, food for thought...


      Thanks!

      A big thanks to Dick Benson, W1QG, who let me modify one of his Matlab routines for this testing and who provided a great sounding board for some of the ideas I had.

      And a big thanks to Russ Sherry, NM6DX, whose comments and insight were invaluable.


      Here's a link to the next post in this series:  http://k6jca.blogspot.com/2015/12/antenna-auto-tuner-design-part-8-build.html

      And please note:  The "final" schematics could have changed from the versions included above, in this post.  The final "release" schematics can be found in Part 10 of this series:  http://k6jca.blogspot.com/2016/01/antenna-auto-tuner-design-part-10-final.html


      Links to my blog posts in this Auto-tuner series:

      Part 1:  Preliminary Specification

      Part 2:  Network Capacitor Selection

      Part 3:  Network Inductor Selection

      Part 4:  Relays and L-Network Schematic (Preliminary)

      Part 5:  Directional Coupler Design

      Part 6:  Notes on Match Detection

      Part 7:  The Build, Phase 1

      Part 8:  The Build, Phase 2 (Integration of Match Detection)

      Part 9:  The Build, Phase 3 (Incorporating a Microcontroller)

      Part 10:  The Final Schematics


      Links to my Directional Coupler blog posts:

      Notes on the Bruene Coupler, Part 2

      Notes on the Bruene Coupler, Part 1

      Notes on HF Directional Couplers

      Building an HF Directional Coupler

      Notes on the Bird Wattmeter

      Notes on the Monimatch

      Notes on the Twin-lead "Twin-Lamp" SWR Indicator

      Calculating Flux Density in Tandem-Match Transformers


      Standard Caveat:

      As always, I might have made a mistake in my equations, assumptions, drawings, or interpretations.  If you see anything you believe to be in error or if anything is confusing, please feel free to contact me or comment below.

      And so I should add -- this design and any associated information is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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